公开(公告)号：US08693117B1

公开(公告)日：2014-04-08

申请号：US13745703

申请日：2013-01-18

Applicant: Marvell International Ltd.

Inventor： Chi Fung Cheng

IPC: G11B5/02

CPC classification number: G11B5/09 ,  G11B20/10194 ,  G11B20/10222 ,  G11B2220/2516

Abstract: According to an aspect of the present disclosure, a method includes: receiving a plurality of groups of one or more phase signals, each group of phase signals having a different phase relative to other groups of one or more phase signals; generating a plurality of interpolated phase shifted signals based on the plurality of groups of one or more phase signals, wherein the plurality of interpolated phase shifted signals do not have an associated common mode component; receiving data bits and precompensating each data bit in accordance with a given interpolated phase shifted signal; and selecting a precompensated data bit for output.

Abstract translation: 根据本公开的一个方面，一种方法包括：接收多组一个或多个相位信号，每组相位信号相对于一个或多个相位信号的其它组具有不同的相位; 基于所述多个一个或多个相位信号组产生多个内插相移信号，其中所述多个内插相移信号不具有相关联的共模分量; 接收数据比特并根据给定的内插相移信号对每个数据比特进行预补偿; 并选择预补偿的数据位进行输出。

公开(公告)号：US08558580B1

公开(公告)日：2013-10-15

申请号：US13686424

申请日：2012-11-27

Applicant: Marvell International Ltd.

Inventor： Chi Fung Cheng ,  Pantas Sutardja

IPC: G01R29/02

CPC classification number: H03K5/156 ,  G11B5/09 ,  G11B20/10222 ,  G11B2220/2516 ,  H03K5/1252

Abstract: A data channel circuit including an analog to digital converter, a timing loop control circuit, an interpolator circuit, and a deglitch circuit. The analog to digital converter is configured to convert an analog input signal into a corresponding digital signal in accordance with a reference clock signal received from a timing loop. The timing loop control circuit is configured to receive the digital signal from the analog to digital converter, and generate a first clock signal based on the digital signal. The interpolator circuit is configured to receive the first clock signal, and generate a second clock signal based on the first clock signal, and the first clock signal delayed by a predetermined phase delay. The second clock signal has first glitches. The deglitch circuit is configured to, based on the second clock signal, generate the reference clock signal. The reference clock signal does not include the first glitches.

Abstract translation: 包括模数转换器，定时回路控制电路，内插器电路和去掉电路的数据通道电路。 模数转换器被配置为根据从定时回路接收的参考时钟信号将模拟输入信号转换成对应的数字信号。 定时回路控制电路被配置为从模数转换器接收数字信号，并且基于数字信号产生第一时钟信号。 内插器电路被配置为接收第一时钟信号，并且基于第一时钟信号和延迟预定相位延迟的第一时钟信号产生第二时钟信号。 第二个时钟信号有第一个毛刺。 去电泳电路被配置为基于第二时钟信号产生参考时钟信号。 参考时钟信号不包括第一个毛刺。

公开(公告)号：US08638604B1

公开(公告)日：2014-01-28

申请号：US13724275

申请日：2012-12-21

Applicant: Marvell International Ltd.

Inventor： Chi Fung Cheng

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/3431 ,  G11C16/3454

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described technique includes monitoring read-back data from a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a single charge level, the two or more bits corresponding to two or more bit positions; determining estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data; and adjusting one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

Abstract translation: 本公开包括与非易失性存储器有关的系统和技术。 所描述的技术包括监视来自基于一组编程电压可编程的一组存储器单元的读回数据，每个存储器单元被配置为通过单个电荷电平表示两个或更多个位，所述两个或多个位 对应于两个或多个位位置; 基于回读数据确定存储器单元的电平分布的估计平均值和标准偏差值; 以及基于估计的电平分布的平均值和标准偏差来调整一个或多个编程电压，使得比特位置的比特错误率之间的差异减小。

公开(公告)号：US08994407B1

公开(公告)日：2015-03-31

申请号：US14051614

申请日：2013-10-11

Applicant: Marvell International Ltd.

Inventor： Chi Fung Cheng ,  Pantas Sutardja

IPC: G01R29/02 ,  H03K9/08 ,  H03K5/156

CPC classification number: H03K5/156 ,  G11B5/09 ,  G11B20/10222 ,  G11B2220/2516 ,  H03K5/1252

Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

Abstract translation: 系统包括基于第一时钟信号将模拟信号转换为数字信号的ADC。 第一电路基于数字信号产生第二时钟信号。 内插器产生第二时钟信号的相位延迟版本和第三时钟信号。 基于第二时钟信号和相位延迟版本产生第三时钟信号，并且包括从第二时钟信号转换到相位延迟版本。 第三时钟信号包括具有第一脉冲宽度的脉冲和具有第二脉冲宽度的脉冲。 由于从第二时钟信号向第三时钟信号的转变，第二脉冲宽度与第一脉冲宽度不同。 第二电路从第三时钟信号中去除具有第二脉冲宽度的脉冲以产生第一时钟信号。