公开(公告)号：US20120293471A1

公开(公告)日：2012-11-22

申请号：US13521308

申请日：2010-12-01

申请人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G02F1/13454 ,  G02F1/13458 ,  G02F2001/136263 ,  H01L27/124

摘要： A gate driving circuit (60) separated into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1) through (T4) are provided, branch lines (78) that connect clock lines (72, 74) to the TFT elements are provided. Junction lines (79A, 79B) are each extended from the branch line (78A) of interest to electrically connect the branch line (78A) of interest to the TFT elements (T2, T4) provided in the stage (ST(j)) different from the stage (ST (j−1)) where the TFT elements (T1, T3) connected to the branch line (78A) of interest are provided.

摘要翻译： 提供分离为多个级（ST）的栅极驱动电路（60）。 在各级（ST）中，设置TFT元件（T1）至（T4），将时钟线（72,74）连接到TFT元件的支线（78）设置。 各接线（79A，79B）各自从感兴趣的支线（78A）延伸，将感兴趣的分支线（78A）电连接到设置在台（ST（j））中的TFT元件（T2，T4）不同 提供与感兴趣的分支线路（78A）连接的TFT元件（T1，T3）的级（ST（j-1））。

公开(公告)号：US20120229712A1

公开(公告)日：2012-09-13

申请号：US13512350

申请日：2010-08-09

申请人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada

发明人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada

IPC分类号： H04N3/14

CPC分类号： G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/136213 ,  G02F1/136286

摘要： In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.

摘要翻译： 在本液晶显示装置中，常规的第一辅助电容干线430形成为窄，并且第二辅助电容干线440被附加地设置并设置在与基板的周边最接近的位置。 因此，移位寄存器可以从衬底的周边远离，而不会增加整个框架区域，从而移位寄存器不会被密封材料覆盖。 此外，可以减少用于向移位寄存器提供信号的布线区域内用密封材料重叠的区域的范围。

公开(公告)号：US08686980B2

公开(公告)日：2014-04-01

申请号：US13521308

申请日：2010-12-01

申请人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G02F1/13454 ,  G02F1/13458 ,  G02F2001/136263 ,  H01L27/124

摘要： A gate driving circuit (60) separated into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1) through (T4) are provided, branch lines (78) that connect clock lines (72, 74) to the TFT elements are provided. Junction lines (79A, 79B) are each extended from the branch line (78A) of interest to electrically connect the branch line (78A) of interest to the TFT elements (T2, T4) provided in the stage (ST(j)) different from the stage (ST (j−1)) where the TFT elements (T1, T3) connected to the branch line (78A) of interest are provided.

摘要翻译： 提供分离为多个级（ST）的栅极驱动电路（60）。 在各级（ST）中，设置TFT元件（T1）至（T4），将时钟线（72,74）连接到TFT元件的支线（78）设置。 各接线（79A，79B）各自从感兴趣的支线（78A）延伸，将感兴趣的分支线（78A）电连接到设置在台（ST（j））中的TFT元件（T2，T4）不同 提供与感兴趣的分支线路（78A）连接的TFT元件（T1，T3）的级（ST（j-1））。

公开(公告)号：US20130039455A1

公开(公告)日：2013-02-14

申请号：US13642714

申请日：2011-01-21

申请人： Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G11C19/18

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

摘要： A shift register stage includes a first transistor having a capacitor electrode (CAPm) that faces, in a film thickness direction, at least one of source and drain electrodes (Tr4s and Tr4d) of the first transistor in a side opposite to a gate electrode (Tr4g) of the first transistor. One of (i) the capacitor electrode (CAPm) and (ii) the one of the source and drain electrodes (Tr4s and Tr4d) which faces the capacitor electrode (CAPm), is electrically connected to a control electrode of an output transistor of the shift register stage.

摘要翻译： 移位寄存器级包括具有电容器电极（CAPm）的第一晶体管，其在膜厚度方向上与第一晶体管的与栅电极相反的一侧中的至少一个源电极和漏电极（Tr4s和Tr4d） Tr4g）的第一晶体管。 （i）电容器电极（CAPm）和（ii）面对电容器电极（CAPm）的源极和漏极（Tr4s和Tr4d）中的一个电连接到输出晶体管的控制电极 移位寄存器阶段。

公开(公告)号：US20110291097A1

公开(公告)日：2011-12-01

申请号：US13138396

申请日：2009-11-05

申请人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： H01L33/16 ,  H01L29/786

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

摘要： An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

摘要翻译： 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US08780311B2

公开(公告)日：2014-07-15

申请号：US13138396

申请日：2009-11-05

申请人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G02F1/1345 ,  G02F1/1339

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

摘要： An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

摘要翻译： 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US09261741B2

公开(公告)日：2016-02-16

申请号：US13512350

申请日：2010-08-09

申请人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada

发明人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada

IPC分类号： G02F1/1339 ,  G02F1/1362 ,  G02F1/1345

CPC分类号： G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/136213 ,  G02F1/136286

摘要： In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.

摘要翻译： 在本液晶显示装置中，常规的第一辅助电容干线430形成为窄，并且第二辅助电容干线440被附加地设置并设置在与基板的周边最接近的位置。 因此，移位寄存器可以从衬底的周边远离，而不会增加整个框架区域，从而移位寄存器不会被密封材料覆盖。 此外，可以减少用于向移位寄存器提供信号的布线区域内用密封材料重叠的区域的范围。

公开(公告)号：US08400597B2

公开(公告)日：2013-03-19

申请号：US12994499

申请日：2009-03-27

申请人： Junichi Morinaga ,  Katsushige Asada ,  Masahiro Yoshida ,  Tetsuya Fujikawa ,  Katsuhiro Mikumo ,  Kuniko Maeno ,  Ryohki Itoh ,  Satoshi Horiuchi ,  Tatsuji Saitoh ,  Isao Ogasawara ,  Kazunori Tanimoto ,  Katsuhiro Okada ,  Toshiaki Fujihara ,  Masakatsu Tominaga

发明人： Junichi Morinaga ,  Katsushige Asada ,  Masahiro Yoshida ,  Tetsuya Fujikawa ,  Katsuhiro Mikumo ,  Kuniko Maeno ,  Ryohki Itoh ,  Satoshi Horiuchi ,  Tatsuji Saitoh ,  Isao Ogasawara ,  Kazunori Tanimoto ,  Katsuhiro Okada ,  Toshiaki Fujihara ,  Masakatsu Tominaga

IPC分类号： G02F1/1337 ,  G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/1393

摘要： Each of picture elements (14) has a plurality of alignment regions (R1, R2, R3, and R4), in each of which liquid crystal molecules contained in a liquid crystal layer are aligned in a direction that is different from those in the others of the plurality of alignment regions. Each of a plurality of scanning signal lines (32) and a border region (R11 and R12) between corresponding adjacent ones of the plurality of alignment regions (R1, R2, R3, and R4) at least partially overlap each other when viewed from above.

摘要翻译： 每个像素（14）具有多个取向区域（R1，R2，R3和R4），其中液晶层中所含的液晶分子在与其它方向不同的方向上排列 的多个对准区域。 当从上方观察时，多个对准区域（R1，R2，R3和R4）中相应的相邻的对齐区域（R1，R2，R3和R4）之间的多个扫描信号线（32）和边界区域（R11和R12）中的每一个至少部分地彼此重叠 。

公开(公告)号：US08723845B2

公开(公告)日：2014-05-13

申请号：US13574049

申请日：2010-11-26

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G2300/0413 ,  G09G2310/0297 ,  G09G2330/08 ,  H01L27/12 ,  H01L27/124 ,  H01L29/41733

摘要： A signal distribution circuit (3) includes (i) a redundancy TFT element (8) provided so as to have a channel width identical to those of driving TFT elements (7), (ii) first redundancy lines (9a, 9b), (iii) a second redundancy line (10), and (iv) a third redundancy line (11). It is therefore possible to provide a liquid crystal display device including the signal distribution circuit (3) in which, even in a case where a leaking part (a defect part) is generated in any of the driving TFT elements (7), it does not take long to restore the leaking part, and productivity can be improved, the driving TFT elements (7) keeping respective channel widths identical to one another even after the leaking part is restored.

摘要翻译： 信号分配电路（3）包括（i）设置为具有与驱动TFT元件（7）相同的沟道宽度的冗余TFT元件（8），（ii）第一冗余线（9a，9b），（ iii）第二冗余线（10），和（iv）第三冗余线（11）。 因此，可以提供一种包括信号分配电路（3）的液晶显示装置，其中即使在任何驱动TFT元件（7）中产生泄漏部分（缺陷部分）的情况下，也可以 即使在泄漏部分恢复之后，驱动TFT元件（7）保持各个通道宽度彼此相同，也不会耗费时间来恢复泄漏部分，并且可以提高生产率。

公开(公告)号：US20130038583A1

公开(公告)日：2013-02-14

申请号：US13642894

申请日：2011-01-28

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

IPC分类号： G11C19/00 ,  G06F3/038 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).

摘要翻译： 提供一种移位寄存器电路，其包括：第一至第N电路部分（1a，1b）（N是等于或大于2的整数），其中每个电路部分中的多个移位寄存器级（SR1，SR2，...， 。，SRn）级联连接; 和电源线（10b，10c，10e，10f）。 第一至第N电路部分（1a，1b）中的每一个接收用于驱动移位寄存器级（SR1，SR2，...，SRn）的驱动信号（CKA1，CKA2，CKB1，CKB2） 10c，10e，10f）分别用于第一至第N电路部分（1a，1b）。