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    Method and apparatus for handling interrupts through the use of a vector access signal
    1.
    发明授权
    Method and apparatus for handling interrupts through the use of a vector access signal 失效
    通过使用向量存取信号来处理中断的方法和装置

    公开(公告)号：US6115778A

    公开(公告)日：2000-09-05

    申请号：US100244

    申请日：1998-06-19

    申请人： Masakazu Miyake ,  Moriyasu Banno ,  Hiroyuki Watanabe

    发明人： Masakazu Miyake ,  Moriyasu Banno ,  Hiroyuki Watanabe

    IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F13/26

    CPC分类号： G06F13/24

    摘要： A control system comprises an interrupt controller, having vector access signal output mechanism for outputting a vector access signal, which is activated when a start address is read out from a vector holder, and a central processing unit (CPU), comprising a present mask holder, which holds a present mask level, and a previous mask holder, which holds a previous mask level, wherein the CPU compares the interrupt level and the present mask level, and, when the interrupt level is higher than the present mask level, copies a value of the present mask level holder into the previous mask level holder, reads out a start address of an interrupt processing program corresponding to an accepted interrupt request from the vector holder, starts executing the interrupt processing program, and copies the interrupt level into a present mask level holder by means of an activated vector access signal.

    摘要翻译： 控制系统包括中断控制器，具有用于输出矢量存取信号的矢量存取信号输出机构，所述矢量存取信号输出机构在从矢量保持器读出起始地址时被激活;以及中央处理单元（CPU） ，其保持当前掩码级别，以及保持先前掩码级别的先前掩码保持器，其中CPU比较中断级别和当前掩码级别，并且当中断级别高于当前掩码级别时，复制一 当前屏蔽级别保持器的值到先前的屏蔽级别保持器中，从向量保持器读出对应于接受的中断请求的中断处理程序的开始地址，开始执行中断处理程序，并将中断级别复制到现在 通过激活的向量访问信号来进行掩模级别保持。

    ADC TEST CIRCUIT AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    ADC TEST CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开
    ADC测试电路和半导体器件

    公开(公告)号：US20100103006A1

    公开(公告)日：2010-04-29

    申请号：US12563501

    申请日：2009-09-21

    申请人： Masakazu Miyake ,  Kazutoshi Shimizu

    发明人： Masakazu Miyake ,  Kazutoshi Shimizu

    IPC分类号： H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/109 ,  H03M1/12

    摘要： An ADC test circuit has an expected value generator configured to generate an expected value signal for a converted output signal of an ADC (Analog to Digital Converter), a test signal generator configured to generate an input test signal applied to the ADC based on the expected value signal, and a comparator configured to compare the converted output signal of the ADC corresponding to the applied input test signal with the expected value signal.

    摘要翻译： ADC测试电路具有期望值发生器，其被配置为产生用于ADC（模数转换器）的转换的输出信号的期望值信号，测试信号发生器被配置为基于所预期的来产生施加到ADC的输入测试信号 以及比较器，被配置为将与所施加的输入测试信号相对应的ADC的转换的输出信号与期望值信号进行比较。