公开(公告)号：US07287155B2

公开(公告)日：2007-10-23

申请号：US10878284

申请日：2004-06-29

申请人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

发明人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

IPC分类号： G06F9/00 ,  G06F11/00

CPC分类号： G06F11/1417

摘要： A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

摘要翻译： PLD插入在微处理器（以下称为MP）和引导存储器之间的通信路由上。 启动存储器存储启动MP所需的MP启动数据和构成MP启动数据的保护代码的启动保护代码。 PLD从引导存储器读取MP启动数据及其启动保护代码，以硬件方式执行使用该启动保护代码检查MP启动数据的有效性，并且如果 获得负检查结果，复位MP，如果获得正检查结果，则将由此读取的启动数据输入到MP。

公开(公告)号：US07644263B2

公开(公告)日：2010-01-05

申请号：US11873995

申请日：2007-10-17

申请人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

发明人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F11/00

CPC分类号： G06F11/1417

摘要： A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

摘要翻译： PLD插入在微处理器（以下称为MP）和引导存储器之间的通信路由上。 启动存储器存储启动MP所需的MP启动数据和构成MP启动数据的保护代码的启动保护代码。 PLD从引导存储器读取MP启动数据及其启动保护代码，以硬件方式执行使用该启动保护代码检查MP启动数据的有效性，并且如果 获得负检查结果，复位MP，如果获得正检查结果，则将由此读取的启动数据输入到MP。

公开(公告)号：US20050235138A1

公开(公告)日：2005-10-20

申请号：US10878284

申请日：2004-06-29

申请人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

发明人： Masanori Fujii ,  Yasuo Inoue ,  Nobuyuki Minowa

IPC分类号： G06F9/445 ,  G06F11/10 ,  G06F11/14 ,  G06F15/177

CPC分类号： G06F11/1417

摘要： A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

摘要翻译： PLD插入在微处理器（以下称为MP）和引导存储器之间的通信路由上。 启动存储器存储启动MP所需的MP启动数据和构成MP启动数据的保护代码的启动保护代码。 PLD从引导存储器读取MP启动数据及其启动保护代码，以硬件方式执行使用该启动保护代码检查MP启动数据的有效性，并且如果 获得负检查结果，复位MP，如果获得正检查结果，则将由此读取的启动数据输入到MP。

公开(公告)号：US20080046672A1

公开(公告)日：2008-02-21

申请号：US11873995

申请日：2007-10-17

申请人： Masanori FUJII ,  Yasuo Inoue ,  Nobuyuki Minowa

发明人： Masanori FUJII ,  Yasuo Inoue ,  Nobuyuki Minowa

IPC分类号： G06F12/00

CPC分类号： G06F11/1417

摘要： A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

摘要翻译： PLD插入在微处理器（以下称为MP）和引导存储器之间的通信路由上。 启动存储器存储启动MP所需的MP启动数据和构成MP启动数据的保护代码的启动保护代码。 PLD从引导存储器读取MP启动数据及其启动保护代码，以硬件方式执行使用该启动保护代码检查MP启动数据的有效性，并且如果 获得负检查结果，复位MP，如果获得正检查结果，则将由此读取的启动数据输入到MP。

公开(公告)号：US07111120B2

公开(公告)日：2006-09-19

申请号：US11188004

申请日：2005-07-25

申请人： Kazuhisa Fujimoto ,  Akira Fujibayashi ,  Nobuyuki Minowa

发明人： Kazuhisa Fujimoto ,  Akira Fujibayashi ,  Nobuyuki Minowa

IPC分类号： G06F12/00

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0689 ,  G06F11/1666 ,  G06F11/2007 ,  G06F11/201 ,  G06F12/084 ,  G06F12/0866

摘要： This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed.Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed.A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.

摘要翻译： 本发明涉及一种磁盘阵列控制器。 需要大量的存储器件系统可操作而不中断。 此外，为了应对最近开放系统的趋势，需要这种系统的性能和容量的可扩展性。 通常，将一个将通道接口部分连接到共享存储器部分的内部总线和共享存储器部分的盘接口部分安装在一个盘片上，并且其上安装了通道接口和其他包装。 如果内部总线出现故障，整个系统的运行必须停止。 另外还有一个问题是内部总线的性能是固定的。 根据本发明的磁盘阵列控制器包括其上安装有通道接口部分和磁盘接口部分的接口拼盘，其上安装有共享存储器部分的存储器盘片和将接口盘连接到存储器盘片的电缆 以解决上述问题。

公开(公告)号：US07042735B2

公开(公告)日：2006-05-09

申请号：US10766848

申请日：2004-01-30

申请人： Tsutomu Koga ,  Mitsuru Inoue ,  Nobuyuki Minowa

发明人： Tsutomu Koga ,  Mitsuru Inoue ,  Nobuyuki Minowa

IPC分类号： H01R12/16

CPC分类号： H05K7/1459

摘要： The invention efficiently mounts substrates to back planes and accomplishes high quality signal transfer. Connectors to which N adaptor substrates are fitted and connectors to which M bus switch substrates are fitted are provided to a multi-layered back plane. Signal pin groups of the connector on the adaptor substrate side are grouped into M data paths. Signal pins of the connector on the adaptor substrate side and corresponding signal pins of the connector on the bus switch substrate side are arranged horizontally in such a fashion as to exist on the same plane (with positions in a Z direction being substantially equal). Therefore, wiring patterns for connecting corresponding signal pins can be formed substantially linearly and a large number of substrates can be efficiently mounted to a limited area.

摘要翻译： 本发明有效地将基板安装到背板并实现高质量的信号传输。 连接有N个适配器基板的连接器以及配有M总线开关基板的连接器提供给多层背板。 适配器基板侧的连接器的信号引脚组被分组为M个数据路径。 适配器基板侧的连接器的信号引脚和总线开关基板侧的连接器的对应的信号引脚以水平方式布置成存在于同一平面上（Z方向上的位置基本相等）。 因此，可以基本上线性地形成用于连接对应的信号引脚的布线图案，并且可以有限地将大量的基板有效地安装到有限的区域。

公开(公告)号：US06981093B2

公开(公告)日：2005-12-27

申请号：US10355087

申请日：2003-01-31

申请人： Nobuyuki Minowa ,  Yoshinori Okubo ,  Yasuhiro Igarashi

发明人： Nobuyuki Minowa ,  Yoshinori Okubo ,  Yasuhiro Igarashi

IPC分类号： G06F12/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16 ,  G11B20/10

CPC分类号： G06F11/1441 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0689 ,  G06F11/2015

摘要： In a disk array control apparatus having a plurality of magnetic disk apparatus under its command for controlling data transfers to and from a host computer in a multiprocessor configuration comprising a plurality of microprocessors, a data path is provided between a cache unit and a shared memory unit, provided independent of the cache unit, for storing configurational information and the like required for system operation and control by the microprocessors, so that in the event of trouble with the apparatus or a sudden abnormality in main power supply, configurational information in a volatile shared memory unit is saved into non-volatile magnetic disk apparatuses from the data path via the cache unit by utilizing an uninterrupted power supply apparatus (UPS).

摘要翻译： 在具有多个磁盘装置的磁盘阵列控制装置中，在包括多个微处理器的多处理器配置中，用于控制到主机计算机的数据传送和从主计算机的数据传输，在高速缓存单元和共享存储器单元之间提供数据通路 独立于高速缓存单元，用于存储由微处理器进行的系统操作和控制所需的配置信息等，使得在设备出现故障或主电源突然异常的情况下，易失性共享的配置信息 存储单元通过使用不间断电源装置（UPS）经由高速缓存单元从数据路径保存到非易失性磁盘装置中。

公开(公告)号：US20050083666A1

公开(公告)日：2005-04-21

申请号：US10766848

申请日：2004-01-30

申请人： Tsutomu Koga ,  Mitsuru Inoue ,  Nobuyuki Minowa

发明人： Tsutomu Koga ,  Mitsuru Inoue ,  Nobuyuki Minowa

IPC分类号： G06F1/18 ,  H05K1/02 ,  H05K1/14 ,  H05K7/06 ,  H05K7/14

CPC分类号： H05K7/1459

摘要： The invention efficiently mounts substrates to back planes and accomplishes high quality signal transfer. Connectors to which N adaptor substrates are fitted and connectors to which M bus switch substrates are fitted are provided to a multi-layered back plane. Signal pin groups of the connector on the adaptor substrate side are grouped into M data paths. Signal pins of the connector on the adaptor substrate side and corresponding signal pins of the connector on the bus switch substrate side are arranged horizontally in such a fashion as to exist on the same plane (with positions in a Z direction being substantially equal). Therefore, wiring patterns for connecting corresponding signal pins can be formed substantially linearly and a large number of substrates can be efficiently mounted to a limited area.

摘要翻译： 本发明有效地将基板安装到背板并实现高质量的信号传输。 连接有N个适配器基板的连接器以及配有M总线开关基板的连接器提供给多层背板。 适配器基板侧的连接器的信号引脚组被分组为M个数据路径。 适配器基板侧的连接器的信号引脚和总线开关基板侧的连接器的对应的信号引脚以水平方式布置成存在于同一平面上（Z方向上的位置基本相等）。 因此，可以基本上线性地形成用于连接对应的信号引脚的布线图案，并且可以有限地将大量的基板有效地安装到有限的区域。

公开(公告)号：US20120246521A1

公开(公告)日：2012-09-27

申请号：US13122695

申请日：2011-03-23

申请人： Koji Washiya ,  Tsutomu Koga ,  Nobuyuki Minowa

发明人： Koji Washiya ,  Tsutomu Koga ,  Nobuyuki Minowa

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/0727 ,  H04L41/0672 ,  H04L41/0677

摘要： Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location.A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.

摘要翻译： 通过及时识别故障位置，可以防止归因于故障发生的数据处理能力的降低。 存储装置包括连接到存储从主机系统发送的数据的存储介质的多个扩展器和用于控制扩展器的控制器，其中控制器向多个扩展器发送故障检测命令; 多个扩展器将命令存储在它们自己的存储单元中; 并且如果多个扩展器中的一个扩展器检测到紧跟在一个扩展器之后的另一扩展器中的故障，则一个扩展器读取存储在一个扩展器的存储单元中的命令，并发送包括对应于 命令给控制器。

公开(公告)号：US20110246720A1

公开(公告)日：2011-10-06

申请号：US12668721

申请日：2009-11-10

申请人： Shuji Nakamura ,  Emi Nakamura ,  Masahiro Arai ,  Hideaki Fukuda ,  Nobuyuki Minowa

发明人： Shuji Nakamura ,  Emi Nakamura ,  Masahiro Arai ,  Hideaki Fukuda ,  Nobuyuki Minowa

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0813 ,  G06F12/0868 ,  G06F2212/284 ,  G06F2212/286

摘要： A first controller, and a second controller coupled to the first controller via a first path are provided. The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.

摘要翻译： 提供了经由第一路径耦合到第一控制器的第一控制器和第二控制器。 第一控制器包括作为控制数据传输的电路的第一继电器电路和经由第一第二路径耦合到第一继电器电路的第一处理器。 第二控制器包括第二继电器电路，其是控制数据传输并且经由第一路径耦合到第一继电器电路的电路，以及经由第二第二路径耦合到第二继电器电路的第二处理器。 第一处理器不是经由第一继电器电路而是经由第一第三路径耦合到第二继电器电路，并且在I / O过程期间经由第一第三路径访问第二继电器电路。 第二处理器不经由第二继电器电路而经由第二第三路径耦合到第一继电器电路，并且在I / O过程期间经由第二第三路径访问第一继电器电路。