-
公开(公告)号：US4908681A
公开(公告)日：1990-03-13
申请号：US265338
申请日：1988-10-27
CPC分类号： H01L29/105 , H01L29/0847 , H01L29/1033
摘要： An insulated gate field effect transistor fabricated in one conductivity type semiconductor substrate wherein a source region and a drain region are formed apart each other to define a channel region therebetween, having a deep ion implantation region which is so formed in the lower portion of the channel region that at least one end portion of the depletion region of the channel extends towards the source region beyond the border between the source region and the channel region at the surface of the substrate whereby an imaginary straight line drawn from said border at the surface of the substrate and an intersecting point between the depletion region of the source and the depletion region of the channel region without a back gate bias voltage defines an angle larger than 90.degree. against the surface of the substrate.
摘要翻译： 制造在一个导电型半导体衬底中的绝缘栅场效应晶体管，其中源极区和漏极区形成为彼此分离以在其间限定沟道区，其中具有在沟道的下部形成的深离子注入区 区域，其中通道的耗尽区的至少一个端部朝向源极区域延伸超过衬底的表面处的源极区域和沟道区域之间的边界，由此从在该衬底的表面处的所述边界绘制的假想直线 衬底和源极的耗尽区与沟道区的耗尽区之间的相交点，而不具有背栅极偏置电压，相对于衬底的表面确定大于90°的角度。
-
公开(公告)号：US06683349B1
公开(公告)日：2004-01-27
申请号：US09652892
申请日：2000-08-31
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes a gate electrode 16 on a P type well through a gate oxide film 9, a heavily-doped N+ type source layer 12 formed to be adjacent to the one end of the gate electrode 16, an N+ type drain layer 12 formed apart from the other end of the gate electrode 16, a P type body layer 14 below the gate electrode 16, and a lightly-doped drain layer 10 formed in an area extending from below the gate electrode 16 to the heavily-doped N+ type drain layer 12 so that it is shallow at least below the gate electrode 16 and deep in the vicinity of the heavily-doped N-type drain layer 12.
摘要翻译： 半导体器件包括通过栅极氧化膜9的P型阱上的栅极16，形成为与栅电极16的一端形成的重掺杂N +型源极层12，形成N +型漏极层12 除了栅电极16的另一端之外，在栅电极16下面的P型体层14和形成在从栅电极16的下方延伸到重掺杂N +型漏极的区域中的轻掺杂漏层10 层12，使得其至少在栅极电极16的下方是浅的，并且深度在重掺杂的N型漏极层12附近。
-
公开(公告)号：US20050118765A1
公开(公告)日：2005-06-02
申请号：US10806610
申请日：2004-03-23
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L31/072
CPC分类号： H01L29/7835 , H01L21/823814 , H01L27/0922 , H01L29/1033 , H01L29/7833
摘要： This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.
摘要翻译： 本发明的特征在于，分别形成在P型阱3上的栅电极27F经由栅极氧化膜9，高浓度N型源极层和分别形成的高浓度N型漏极层15 分别形成为分别围绕N型源极层和N型漏极层10的低浓度N型源极层和低浓度N型源极层以及分别由 提供了形成在栅电极27F下面的P型体层。
-
公开(公告)号：US06784059B1
公开(公告)日：2004-08-31
申请号：US09652044
申请日：2000-08-31
IPC分类号： H01L218234
CPC分类号： H01L29/7835 , H01L21/823814 , H01L27/0922 , H01L29/1033 , H01L29/7833
摘要： This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.
摘要翻译： 本发明的特征在于，经由栅极氧化膜9形成在P型阱3上的栅极27F，高浓度N型源极层和高浓度N型漏极层15 分别形成为分别围绕N型源极层和N型漏极层10的栅极电极和低浓度N型源极层以及低浓度H型漏极层，分别由P 设置形成在栅电极27F下方的主体层。
-
公开(公告)号：US06635925B1
公开(公告)日：2003-10-21
申请号：US09652891
申请日：2000-08-31
IPC分类号： H01L2976
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A P-channel type DMOS transistor includes heavily doped source/drain layers 12 formed in an N-type well 2, a gate electrode 18 formed on a channel layer located between the source/drain layers 12, an N-type body layer 14 formed in the vicinity of the source layer, and a lightly-doped drain layer 6 formed between the channel layer and the drain layer 12. In such a P-channel type DMOS transistor, a P-type layer 16 is formed in the channel layer at the upper part of the N-type body layer 14. In this configuration, the driving capability of the P-channel type DMOS transistor can be improved.
摘要翻译： P沟道型DMOS晶体管包括形成在N型阱2中的重掺杂源极/漏极层12，形成在位于源/漏层12之间的沟道层上的栅电极18，形成的N型体层14 在源极层附近，以及形成在沟道层和漏极层12之间的轻掺杂漏极层6.在这种P沟道型DMOS晶体管中，在沟道层中形成P型层16 N型体层14的上部。在该结构中，可以提高P沟道型DMOS晶体管的驱动能力。
-
公开(公告)号：US07224023B2
公开(公告)日：2007-05-29
申请号：US10806610
申请日：2004-03-23
IPC分类号： H01L29/76 , H01L31/113 , H01L31/062 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7835 , H01L21/823814 , H01L27/0922 , H01L29/1033 , H01L29/7833
摘要： This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.
摘要翻译： 本发明的特征在于，分别形成在P型阱3上的栅电极27F经由栅极氧化膜9，高浓度N型源极层和分别形成的高浓度N型漏极层15 分别形成为分别围绕N型源极层和N型漏极层10的低浓度N型源极层和低浓度N型源极层以及分别由 提供了形成在栅电极27F下面的P型体层。
-
公开(公告)号：US5940708A
公开(公告)日：1999-08-17
申请号：US690485
申请日：1996-07-31
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66659 , H01L21/823864 , H01L27/0922 , H01L29/7835
摘要： A method for the production of a semiconductor integrated circuit device is disclosed, wherein the formation of lateral wall spacers for high voltage MOS transistor is implemented by forming a resist film for covering at least an insulating film formed on a drain region of low impurity concentration in the proximity of a gate electrode, masking the resist film, and etching the parts of the insulating film destined to give rise to the lateral wall spacers.
摘要翻译： 公开了一种制造半导体集成电路器件的方法，其中通过形成用于覆盖形成在低杂质浓度的漏区上的至少绝缘膜的抗蚀剂膜来实现用于高压MOS晶体管的侧壁间隔物的形成 栅电极的接近，掩模抗蚀剂膜，以及蚀刻绝缘膜的部分，以产生侧壁间隔物。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.017 秒)
