公开(公告)号：US5402376A

公开(公告)日：1995-03-28

申请号：US103781

申请日：1993-08-10

申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/832 ,  G11C5/14

摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

摘要翻译： 在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。 另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。 开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。 然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

公开(公告)号：US5677880A

公开(公告)日：1997-10-14

申请号：US407850

申请日：1995-03-21

申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/832 ,  G11C5/14

摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

摘要翻译： 在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。 另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。 开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。 然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

公开(公告)号：US4994688A

公开(公告)日：1991-02-19

申请号：US323966

申请日：1989-03-15

申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02

CPC分类号： G11C5/147 ,  G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  H01L27/0203 ,  Y10S323/907

摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

摘要翻译： 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5179539A

公开(公告)日：1993-01-12

申请号：US865677

申请日：1992-04-08

申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02

CPC分类号： G11C5/147 ,  G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  H01L27/0203

摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

摘要翻译： 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5376839A

公开(公告)日：1994-12-27

申请号：US104340

申请日：1993-08-09

申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H03K3/01 ,  H03K3/26

CPC分类号： G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  G11C5/147 ,  H01L27/0203

摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

摘要翻译： 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5262993A

公开(公告)日：1993-11-16

申请号：US789024

申请日：1991-11-06

申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/832 ,  G11C5/14

摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

摘要翻译： 在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。 另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。 开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。 然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

公开(公告)号：US5254880A

公开(公告)日：1993-10-19

申请号：US863705

申请日：1992-04-03

申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin ichi Ikenaga

发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin ichi Ikenaga

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H03K3/01 ,  H03K5/01

CPC分类号： G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  G11C5/147 ,  H01L27/0203

摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

摘要翻译： 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5272393A

公开(公告)日：1993-12-21

申请号：US790065

申请日：1991-11-12

申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

IPC分类号： G05F1/46 ,  H03K17/693 ,  H03K3/01 ,  H03K5/22

CPC分类号： H03K17/693 ,  G05F1/465

摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.

摘要翻译： 在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。 所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。 差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

公开(公告)号：US5528548A

公开(公告)日：1996-06-18

申请号：US384962

申请日：1995-02-07

申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

IPC分类号： G05F1/46 ,  H03K17/693 ,  G11C7/00

CPC分类号： H03K17/693 ,  G05F1/465

摘要： A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.

摘要翻译： 提供一种半导体存储器，其包括电压转换器，其向半导体存储器中的电路提供与两个参考电压中的较大一个成比例的内部电源电压。 电压转换器包括电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一电路用于产生对外部供电电压的依赖性大于 第一电压的依赖性。 电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压电路。 该存储器还包括用于升高内部电源电压的字线升压器。

公开(公告)号：US5402375A

公开(公告)日：1995-03-28

申请号：US207679

申请日：1994-03-09

申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

IPC分类号： G05F1/46 ,  H03K17/693 ,  G11C7/00

CPC分类号： H03K17/693 ,  G05F1/465

摘要： In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.

摘要翻译： 在设置在半导体存储器中的电压转换器中并向半导体存储器中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压装置。 该存储器还包括用于升高内部电源电压的字线升压器。