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    Low noise semiconductor memory
    4.
    发明授权
    Low noise semiconductor memory 失效
    低噪声半导体存储器

    公开(公告)号：US4958325A

    公开(公告)日：1990-09-18

    申请号：US238375

    申请日：1988-08-31

    申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

    发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

    IPC分类号： G11C7/18 ,  G11C11/4097

    CPC分类号： G11C7/18 ,  G11C11/4097

    摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.

    摘要翻译： 高度集成的半导体存储器，特别是低噪声动态存储器。 随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。 为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置， 与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置 差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测 放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压 她的数据线是一对低电平的电压。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5475692A

    公开(公告)日：1995-12-12

    申请号：US407986

    申请日：1995-03-22

    申请人： Susumu Hatano ,  Jun Kitano ,  Kenji Nishimoto ,  Shin'ichi Ikenaga ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Takeshi Wada ,  Michihiro Mishima ,  Fujio Yamamoto

    发明人： Susumu Hatano ,  Jun Kitano ,  Kenji Nishimoto ,  Shin'ichi Ikenaga ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Takeshi Wada ,  Michihiro Mishima ,  Fujio Yamamoto

    IPC分类号： G11C29/10 ,  G11C29/14 ,  G11C29/40 ,  G06F11/00

    CPC分类号： G11C29/40 ,  G11C29/10 ,  G11C29/14

    摘要： Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

    摘要翻译： 这里公开了一种半导体集成电路，用于测试所有位的两种非反相和反相状态的测试数据，其中一种预期数据可以压缩并输出测试结果。 半导体集成电路包括：决定电路25，用于决定第一状态，其中由模式寄存器锁存的预期数据和存储单元阵列的读取数据一致;第二状态，读取数据与 逻辑反转的预期数据的数据，以及通过异或门以外的第一状态和第二状态的第三状态，以产生能够区分各个状态的2位的信号。 这些状态根据高低电平和高阻抗通知到半导体集成电路的外部。