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    Low noise semiconductor memory
    5.
    发明授权
    Low noise semiconductor memory 失效
    低噪声半导体存储器

    公开(公告)号：US4958325A

    公开(公告)日：1990-09-18

    申请号：US238375

    申请日：1988-08-31

    申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

    发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

    IPC分类号： G11C7/18 ,  G11C11/4097

    CPC分类号： G11C7/18 ,  G11C11/4097

    摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.

    摘要翻译： 高度集成的半导体存储器，特别是低噪声动态存储器。 随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。 为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置， 与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置 差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测 放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压 她的数据线是一对低电平的电压。

    Voltage converter of semiconductor device
    10.
    发明授权
    Voltage converter of semiconductor device 失效
    半导体器件的电压转换器

    公开(公告)号：US5272393A

    公开(公告)日：1993-12-21

    申请号：US790065

    申请日：1991-11-12

    申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    IPC分类号： G05F1/46 ,  H03K17/693 ,  H03K3/01 ,  H03K5/22

    CPC分类号： H03K17/693 ,  G05F1/465

    摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.

    摘要翻译： 在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。 所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。 差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。