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149 条记录 (耗时 0.027 秒)

    Joint connector
    1.
    发明授权
    Joint connector 有权
    接头连接器

    公开(公告)号：US08690607B2

    公开(公告)日：2014-04-08

    申请号：US13569823

    申请日：2012-08-08

    申请人： Masashi Tsukamoto ,  Yoshihiro Murakami

    发明人： Masashi Tsukamoto ,  Yoshihiro Murakami

    IPC分类号： H01R13/66

    CPC分类号： H01R31/08 ,  H01R13/7193 ,  H01R2201/26

    摘要： For providing a joint connector which is miniaturized and general-purpose by designing an interval between needle shape terminal portions same as an interval between terminals of the general-purpose connector, the joint connector 1 includes a terminal 3 with a ferrite core 10, and a connector housing 2 receiving the terminal 3. The terminal 3 includes a busbar 28 and a plurality of needle shape terminal portions 29 extending from the busbar 28 at intervals along a direction of lengthwise of the busbar 28. The ferrite core 10 includes a first ferrite core 10a arranged at a base end 29a of the needle shape terminal portion 29 and a second ferrite core 10b arranged at an intermediate portion 29b of the needle shape terminal portion 29. The first ferrite core 10a and the second ferrite core 10b are arranged alternately at each of the plurality of needle shape terminal portions 29.

    摘要翻译： 为了通过设计与通用连接器的端子之间的间隔相同的针形端子部之间的间隔来提供小型化和通用的接头连接器，接头连接器1包括具有铁氧体磁芯10的端子3和 连接器壳体2接收端子3.端子3包括母线28和从母线28沿着母线28的长度方向间隔地延伸的多个针状端子部29.铁氧体磁芯10包括第一铁氧体磁芯 10a布置在针形端子部分29的基端29a处，第二铁氧体芯10b布置在针状端子部分29的中间部分29b处。第一铁氧体磁芯10a和第二铁氧体磁心10b每个交替布置 的多个针状端子部29。

    JOINT CONNECTOR
    2.
    发明申请
    JOINT CONNECTOR 有权
    接头连接器

    公开(公告)号：US20140045381A1

    公开(公告)日：2014-02-13

    申请号：US13569823

    申请日：2012-08-08

    申请人： Masashi Tsukamoto ,  Yoshihiro Murakami

    发明人： Masashi Tsukamoto ,  Yoshihiro Murakami

    IPC分类号： H01R24/66

    CPC分类号： H01R31/08 ,  H01R13/7193 ,  H01R2201/26

    摘要： For providing a joint connector which is miniaturized and general-purpose by designing an interval between needle shape terminal portions same as an interval between terminals of the general-purpose connector, the joint connector 1 includes a terminal 3 with a ferrite core 10, and a connector housing 2 receiving the terminal 3. The terminal 3 includes a busbar 28 and a plurality of needle shape terminal portions 29 extending from the busbar 28 at intervals along a direction of lengthwise of the busbar 28. The ferrite core 10 includes a first ferrite core 10a arranged at abase end 29a of the needle shape terminal portion 29 and a second ferrite core 10b arranged at an intermediate portion 29b of the needle shape terminal portion 29. The first ferrite core 10a and the second ferrite core 10b are arranged alternately at each of the plurality of needle shape terminal portions 29.

    摘要翻译： 为了通过设计与通用连接器的端子之间的间隔相同的针形端子部之间的间隔来提供小型化和通用的接头连接器，接头连接器1包括具有铁氧体磁芯10的端子3和 连接器壳体2接收端子3.端子3包括母线28和从母线28沿着母线28的长度方向间隔地延伸的多个针状端子部29.铁氧体磁芯10包括第一铁氧体磁芯 10a设置在针形端子部29的下端29a处，布置在针状端子部29的中间部29b处的第二铁氧体磁芯10b。第一铁氧体磁芯10a和第二铁氧体磁芯10b 多个针状端子部29。

    Apparatus and method for face recognition and computer program
    4.
    发明授权
    Apparatus and method for face recognition and computer program 失效
    面部识别和计算机程序的装置和方法

    公开(公告)号：US08396262B2

    公开(公告)日：2013-03-12

    申请号：US12049744

    申请日：2008-03-17

    申请人： Kazuki Aisaka ,  Yoshihiro Murakami

    发明人： Kazuki Aisaka ,  Yoshihiro Murakami

    IPC分类号： G06K9/00 ,  H04N5/225 ,  H04N7/18 ,  G05B19/00

    CPC分类号： G06K9/00261 ,  G06K9/6255 ,  Y10T82/17

    摘要： Disclosed is a face recognition apparatus for previously registering a face image of a person, receiving a moving image in which face identification is intended to be performed, and performing face recognition in the received moving image. The apparatus includes the following elements. A face registration unit registers the face of a person as an image. A face detection unit detects a face in a frame of an input moving image. A face tracking unit tracks the detected face in frames of the input moving image. A face identification unit compares the detected face, which is being tracked by the face tracking unit, with the registered face registered in the face registration unit to identify the face. A stabilization unit stabilizes the result of face identification by the face identification unit.

    摘要翻译： 公开了一种面部识别装置，用于预先登记人的面部图像，接收要进行脸部识别的运动图像，并在接收到的运动图像中进行面部识别。 该装置包括以下元件。 面部登记单元将人的面部登记为图像。 面部检测单元检测输入运动图像的帧中的脸部。 面部跟踪单元以输入运动图像的帧为单位跟踪检测到的面部。 面部识别单元将由脸部跟踪单元跟踪的检测到的脸部与登记在面部登记单元中的登记脸部进行比较，以识别脸部。 稳定单元通过面部识别单元稳定脸部识别的结果。

    METHOD TO INCREASE THE ACCURACY OF PHASE CORRELATION MOTION ESTIMATION IN LOW-BIT-PRECISION CIRCUMSTANCES
    6.
    发明申请
    METHOD TO INCREASE THE ACCURACY OF PHASE CORRELATION MOTION ESTIMATION IN LOW-BIT-PRECISION CIRCUMSTANCES 有权
    提高低位精密电路相位运动估计精度的方法

    公开(公告)号：US20120098985A1

    公开(公告)日：2012-04-26

    申请号：US12912536

    申请日：2010-10-26

    申请人： Mark Robertson ,  Ming-Chang Liu ,  Yoshihiro Murakami ,  Toru Kurata ,  Yutaka Yoneda

    发明人： Mark Robertson ,  Ming-Chang Liu ,  Yoshihiro Murakami ,  Toru Kurata ,  Yutaka Yoneda

    IPC分类号： H04N5/14 ,  H04N5/225

    CPC分类号： H04N5/145 ,  G06T7/262 ,  G06T2207/20021 ,  G06T2207/20056

    摘要： A method and system to improve the performance of phase correlation motion estimation for low-bit-precision implementation are described herein. Phase correlation uses the Fast Fourier Transform (FFT) with operations with infinite-precision constants. Since physical implementations use finite-precision arithmetic, there is some loss in precision relative to the ideal infinite-precision case. In low-complexity implementations, it is desirable to use as few bits as possible, and if the precision is too low, the performance of traditional phase correlation suffers. A pre-processing technique is applied to the data prior to taking the FFT, which minimizes the negative effects of finite precision in the FFT and allows high quality results from phase correlation. The pre-processing step is a content-dependent contrast adjustment that maps the range of the input images' pixel values to the range of input values for the FFT. There is no post-processing required after the FFT to compensate for the pre-processing step.

    摘要翻译： 本文描述了一种用于提高低位精度实现的相位运动估计性能的方法和系统。 相位相关使用具有无限精度常数的运算的快速傅里叶变换（FFT）。 由于物理实现使用有限精度算术，相对于理想的无限精度情况，精度有一定的损失。 在低复杂度实现中，期望尽可能少地使用位，如果精度太低，则传统相位相关的性能受损。 在采用FFT之前，将预处理技术应用于数据，这最小化了FFT中有限精度的负面影响，并允许相位相关的高质量结果。 预处理步骤是内容相关的对比度调整，其将输入图像的像素值的范围映射到用于FFT的输入值的范围。 在FFT之后不需要后处理来补偿预处理步骤。

    Data processing apparatus
    7.
    发明授权
    Data processing apparatus 有权
    数据处理装置

    公开(公告)号：US08139615B2

    公开(公告)日：2012-03-20

    申请号：US12106085

    申请日：2008-04-18

    申请人： Yoshihiro Murakami

    发明人： Yoshihiro Murakami

    IPC分类号： H04J3/04

    CPC分类号： G06F13/4059 ,  H04J3/047 ,  H04J3/1605 ,  H04S1/007

    摘要： A data processing apparatus includes a channel demultiplexing circuit, a bus, a memory controller and a memory. The channel demultiplexing circuit has a first delay circuit which delays first channel data only of multi-channel data by one cycle and outputs first delayed channel data, a second delay circuit which delays second channel data only of the multi-channel data by one cycle and outputs second delayed channel data, and a channel data holding circuit which stores first coupled data obtained by coupling the first channel data and the first delayed channel data for multiple cycles and stores second coupled data obtained by coupling the second channel data and an output of the second delay circuit for multiple cycles. The channel demultiplexing circuit selectively outputs a first channel data group and a second channel data group to the bus.

    摘要翻译： 数据处理装置包括信道解复用电路，总线，存储器控制器和存储器。 信道解复用电路具有第一延迟电路，该第一延迟电路仅将多通道数据的第一通道数据延迟一个周期，并输出第一延迟通道数据，第二延迟电路仅将多通道数据的第二通道数据延迟一个周期， 输出第二延迟信道数据，以及信道数据保持电路，其存储通过将第一信道数据和第一延迟信道数据耦合多个周期获得的第一耦合数据，并存储通过耦合第二信道数据获得的第二耦合数据和 第二延迟电路多个周期。 信道解复用电路选择性地向总线输出第一信道数据组和第二信道数据组。

    Memory control circuit and semiconductor integrated circuit incorporating the same
    9.
    发明授权
    Memory control circuit and semiconductor integrated circuit incorporating the same 有权
    存储器控制电路和包含其的半导体集成电路

    公开(公告)号：US07907471B2

    公开(公告)日：2011-03-15

    申请号：US12539144

    申请日：2009-08-11

    申请人： Yoshihiro Murakami

    发明人： Yoshihiro Murakami

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4243 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076

    摘要： A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a significant state of a data strobe signal, which is provided together with the data signal. The memory control circuit controls data acquisition from the retention circuit in accordance with the clock signal. A data acquisition timing judgment unit, by monitoring the clock signal, judges whether or not a timing of the data acquisition has arrived. A data strobe signal correction unit maintains the significant state of the data strobe signal until it is judged that the data acquisition timing has arrived.

    摘要翻译： 存储器控制电路包括产生时钟信号并将时钟信号提供给外部存储器件的时钟产生电路和至少一个保持电路，其保持仅从外部存储器件提供的数据信号处于数据的显着状态 选通信号，与数据信号一起提供。 存储器控制电路根据时钟信号控制从保持电路的数据采集。 数据采集​​定时判断单元，通过监视时钟信号，判定数据采集的定时是否已到。 数据选通信号校正单元维持数据选通信号的显着状态，直到判断数据采集定时已到。