公开(公告)号：US06707102B2

公开(公告)日：2004-03-16

申请号：US09929016

申请日：2001-08-15

申请人： Masatoshi Morikawa ,  Mio Shindo ,  Isao Yoshida ,  Kenichi Nagura

发明人： Masatoshi Morikawa ,  Mio Shindo ,  Isao Yoshida ,  Kenichi Nagura

IPC分类号： H01L2976

CPC分类号： H01L29/402 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/7835 ,  H03F1/565 ,  H03F3/193

摘要： A power MOSFET for a high frequency amplification element having good output power characteristics and high frequency characteristics is described. In the power MOSFET, a shield conductive film electrically connected to via an insulating film is arranged over a drain-offset semiconductor region. A wiring for a drain electrode is so arranged as to extent in parallel to the shield conductive film at one end side of the shield conductive film. On the other hand, a wiring for the gate electrode, a wiring for a source electrode and a gate shunt wiring are arranged in this order to extend in parallel to each other at the other end side of the shield conductive film. The shield conductive film is so formed that the thickness thereof is smaller than that of the wiring for the gate electrode. In this way, the input and output capacitances of the MOSFET can be decreased.

摘要翻译： 描述了具有良好的输出功率特性和高频特性的高频放大元件的功率MOSFET。 在功率MOSFET中，通过绝缘膜电连接的屏蔽导电膜设置在漏极 - 偏移半导体区域上。 用于漏电极的布线被布置成与屏蔽导电膜的一端侧处的屏蔽导电膜平行地设置。 另一方面，用于栅电极的布线，用于源电极的布线和栅极分路布线依次布置成在屏蔽导电膜的另一端侧彼此平行地延伸。 屏蔽导电膜形成为使得其厚度小于栅电极的布线的厚度。 以这种方式，MOSFET的输入和输出电容可以减小。

公开(公告)号：US20060237787A1

公开(公告)日：2006-10-26

申请号：US11475989

申请日：2006-06-28

申请人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

发明人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

IPC分类号： H01L29/76

CPC分类号： H01L29/0653 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835

摘要： In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 μm or less, or a trench of 2 μm or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.

公开(公告)号：US07078765B2

公开(公告)日：2006-07-18

申请号：US10812870

申请日：2004-03-31

申请人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

发明人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

IPC分类号： H01L29/94

CPC分类号： H01L29/0653 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835

摘要： In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 μm or less, or a trench of 2 μm or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.

摘要翻译： 在提高LDMOS的高频功率增益的技术中，从覆盖电极焊盘的钝化膜的表面到硅衬底的后表面的距离设定为200μm或更小，或2μm的沟槽或 当形成ap型杂质扩散的区域时，形成绝缘膜或导体的厚度越多，形成ap + +型源极穿透层的区域， 第三LDMOS，以便从半导体层的前表面向硅衬底延伸。 该沟槽限制了p + SUP +型源极穿透层扩散到沟道区域，从而降低了源极的电感或电阻，并提高了高频功率增益。

公开(公告)号：US07388256B2

公开(公告)日：2008-06-17

申请号：US11475989

申请日：2006-06-28

申请人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

发明人： Kingo Kurotani ,  Takeshi Sakamoto ,  Michio Yano ,  Kenichi Nagura

IPC分类号： H01L29/76

CPC分类号： H01L29/0653 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835

摘要： In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 μm or less, or a trench of 2 μm or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.

摘要翻译： 在提高LDMOS的高频功率增益的技术中，从覆盖电极焊盘的钝化膜的表面到硅衬底的后表面的距离设定为200μm或更小，或2μm的沟槽或 当形成ap型杂质扩散的区域时，形成绝缘膜或导体的厚度越多，形成ap + +型源极穿透层的区域， 第三LDMOS，以便从半导体层的前表面向硅衬底延伸。 该沟槽抑制p + SUP型源极穿透层扩散到沟道区域，从而降低源极的电感或电阻，并提高高频功率增益。