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公开(公告)号：US08050085B2
公开(公告)日：2011-11-01
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。
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公开(公告)号：US20090213649A1
公开(公告)日：2009-08-27
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。
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公开(公告)号：US07228377B2
公开(公告)日：2007-06-05
申请号：US10857888
申请日：2004-06-02
申请人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
发明人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
IPC分类号： G06F12/00
CPC分类号： G06K19/077 , G06F12/0893 , G06F2212/2022 , G11C16/04 , G11C16/0466 , G11C16/102 , G11C16/105 , H01L27/115 , H01L27/11568
摘要： In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.
摘要翻译： 本发明提供了一种能够将EEPROM容量限制在最小必需量并减少芯片面积的技术，其中配备有闪存和EEPROM的半导体集成电路装置是非易失性存储器。 一个应用程序所需的最小尺寸数据和频繁重写的数据存储在EEPROM中，并且EEPROM被配置为具有大约最小尺寸的容量。 由其他应用程序分别处理并经常重写的相同大小的数据被存储在闪速存储器中。 对于实际使用的应用，存储在闪速存储器中的数据被传送到EEPROM并使用。 必要时，执行闪速存储器与EEPROM之间的数据传输。 因此，可以减小EEPROM容量并且可以实现芯片面积的减小。
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4.发明授权公开(公告)号：US07086087B1
公开(公告)日：2006-08-01
申请号：US09599005
申请日：2000-06-22
申请人： Masahiro Kaminaga , Takashi Endo , Masaru Ohki , Takashi Tsukamoto , Hiroshi Watase , Chiaki Terauchi , Kunihiko Nakada , Nobutaka Nagasaki , Satoshi Taira , Yuuichirou Nariyoshi , Yasuko Fukuzawa
发明人： Masahiro Kaminaga , Takashi Endo , Masaru Ohki , Takashi Tsukamoto , Hiroshi Watase , Chiaki Terauchi , Kunihiko Nakada , Nobutaka Nagasaki , Satoshi Taira , Yuuichirou Nariyoshi , Yasuko Fukuzawa
CPC分类号： G07F7/1008 , G06K19/063 , G06Q20/341 , G07F7/082
摘要： It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used. Furthermore, the present invention also provides another data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line wherein, between at least either the first information processing device or the second information processing device and the signal line, a signal from the first information processing device or the second information processing device can be encrypted and a signal received from the signal line can be decrypted. In addition, the present invention also provides a further data processing apparatus comprising at least an information processing device, an information memory device and a signal line connected at least to the information processing device wherein at least in an operation to store information into the information memory device, the information is encrypted, and information stored in the information memory device can be decrypted.
摘要翻译： 本发明的技术目的在于提供具有高安全性的信息处理装置，卡片和卡片系统。 为了实现上述目的，本发明提供了一种数据处理装置，包括至少第一信息处理装置和通过信号线连接到第一信息处理装置的第二信息处理装置，该数据处理装置具有装置 用于根据当不使用装置时将观察到的功耗的实际状态，在通过信号线的信号传输期间改变信号线上的功率消耗。 此外，本发明还提供了另一种数据处理装置，其至少包括通过信号线连接到第一信息处理装置的第一信息处理装置和第二信息处理装置，其中，在至少第一信息处理装置或第二信息处理装置 信息处理装置和信号线，可以加密来自第一信息处理装置或第二信息处理装置的信号，并且可以解密从信号线接收的信号。 另外，本发明还提供了一种数据处理装置，至少包括信息处理装置，信息存储装置和至少连接到信息处理装置的信号线，其中至少在将信息存储到信息存储器中的操作中 信息被加密，并且存储在信息存储装置中的信息可被解密。
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5.发明授权
公开(公告)号：US5179694A
公开(公告)日：1993-01-12
申请号：US577123
申请日：1990-09-04
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
摘要翻译： 由单片机内的时钟发生电路产生的外部同步信号被提供给该芯片的外部端子。 外部同步信号在外部扩展模式下是必需的，但不是单芯片模式。 因此，通过控制栅极将外部同步信号提供给外部端子，同时将合适的控制信号输入到控制栅极的控制端子。 根据该电路结构，可以以这样的方式进行控制，使得外部同步信号不以单芯片模式提供给输出端子。 结果，可以通过单芯片模式中的外部端子之间的耦合容量来防止噪声进入相邻引脚的信号，并且降低输出缓冲电路的消耗功率，该输出缓冲电路设置在控制 门和外部端子。
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公开(公告)号：US5493686A
公开(公告)日：1996-02-20
申请号：US434292
申请日：1995-05-03
CPC分类号： G06F1/10
摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
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7.发明授权
公开(公告)号：US4967352A
公开(公告)日：1990-10-30
申请号：US230047
申请日：1988-08-09
CPC分类号： G06F1/10
摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
摘要翻译： 由单片机内的时钟发生电路产生的外部同步信号被提供给该芯片的外部端子。 外部同步信号在外部扩展模式下是必需的，但不是单芯片模式。 因此，通过控制栅极将外部同步信号提供给外部端子，同时将合适的控制信号输入到控制栅极的控制端子。 根据该电路结构，可以以这样的方式进行控制，使得外部同步信号不以单芯片模式提供给输出端子。 结果，可以通过单芯片模式中的外部端子之间的耦合容量来防止噪声进入提供给相邻引脚的信号，并且降低输出缓冲电路的消耗功率，该输出缓冲电路被布置在控制 门和外部端子。
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公开(公告)号：US5497482A
公开(公告)日：1996-03-05
申请号：US301740
申请日：1994-09-07
CPC分类号： G06F1/10
摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
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