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公开(公告)号：US07068196B2
公开(公告)日：2006-06-27
申请号：US10489947
申请日：2003-07-29
申请人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
发明人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
IPC分类号： H03M3/00
CPC分类号： H03M7/3011 , H03M7/3028 , H03M7/304
摘要： An apparatus for processing a digital signal that generates a one-bit output signal using a delta-sigma modulation apparatus, which includes a quantizer for quantizing an integrated output of a sixth integrator to generate a one-bit output signal that is send to respective integrators through an adder under feedback processing to output the one-bit output signal to the outside of a six-order Delta-sigma modulator, and a control unit for generating a control signal that controls the feedback loop signal from the quantizer so as to change the signal level of a signal component of the audio frequency band of the one-bit output signal. The control unit receives an integrated output from a second integrator being an input side integrator of the six-order delta-sigma modulator.
摘要翻译： 一种用于处理使用delta-sigma调制装置产生1比特输出信号的数字信号的装置，该装置包括用于量化第六积分器的积分输出的量化器，以产生发送给相应积分器的1比特输出信号 通过反馈处理的加法器将一位输出信号输出到六阶Delta-sigma调制器的外部;以及控制单元，用于产生控制信号，该控制信号控制来自量化器的反馈回路信号，以便改变 1位输出信号的音频频带的信号分量的信号电平。 控制单元从作为六阶Δ-Σ调制器的输入侧积分器的第二积分器接收积分输出。
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公开(公告)号：US20050285765A1
公开(公告)日：2005-12-29
申请号：US11151359
申请日：2005-06-14
申请人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
发明人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
CPC分类号： H03M3/36 , H03M3/43 , H03M3/45 , H03M3/454 , H03M7/3011 , H03M7/3028 , H03M7/3033 , H03M7/304
摘要： A delta-sigma modulator and delta-sigma modulation method according to the present invention are capable of ensuring a stable 1-bit signal having less distortion at the transition time from an audio signal reproduction state to soundless state while maintaining high sound quality during reproduction of an audio signal representing music or the like, and, at the same time, capable of maintaining high sound quality at the transition time from a soundless state to audio signal reproduction state. The delta-sigma modulator applies delta-sigma modulation to an input signal to output a 1-bit digital signal, and comprises an integration section that applies integration to the input signal, a quantization section that quantizes the integrated output from the integration section, a random noise generation section that generates a random noise signal whose gain has been adjusted based on the integrated output of the integration section, a detection section that detects a predetermined pattern from the input signal, and a changeover section that switches supply and suspension of supply of the random noise signal from the random noise generation section to the quantization section based on a detection result of the detection section.
摘要翻译： 根据本发明的Δ-Σ调制器和Δ-Σ调制方法能够确保在从音频信号再现状态到无声状态的转变时间具有较小失真的稳定的1比特信号，同时在再现期间保持高音质 表示音乐等的音频信号，并且同时能够在从无声状态到音频信号再现状态的转变时保持高音质。 Δ-Σ调制器对输入信号施加Δ-Σ调制以输出1位数字信号，并且包括对输入信号进行积分的积分部分，对来自积分部分的积分输出进行量化的量化部分， 随机噪声生成部，其生成基于积分部的积分输出调整了增益的随机噪声信号;检测部，其根据所述输入信号检测出规定的图案;以及切换部，切换供给和停止供给 基于检测部的检测结果，从随机噪声生成部到量化部的随机噪声信号。
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3.发明授权公开(公告)号：US07205919B2
公开(公告)日：2007-04-17
申请号：US11073629
申请日：2005-03-08
申请人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
发明人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
IPC分类号： H03M1/66
CPC分类号： H04B14/062
摘要： The present invention aims to realize linking of 1-bit signals having respective sampling frequencies that are different from each other and show a relationship of one equal to integer times of the other without noises.
摘要翻译： 本发明旨在实现具有彼此不同的各采样频率的1比特信号的链接，并且显示出一个等于另一个无噪声的整数倍的关系。
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4.发明申请公开(公告)号：US20060071833A1
公开(公告)日：2006-04-06
申请号：US11219757
申请日：2005-09-07
申请人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
发明人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
IPC分类号： H03M3/00
CPC分类号： G06F7/602 , H03M7/3028 , H03M7/304
摘要： The present invention provides a digital signal processing apparatus which can perform batch processing of mixing and gain controlling, etc., one time while the frequency characteristics of different filters are being mixed to a plurality of input signals in case of the re-quantization only once. The present invention provides a digital signal processing apparatus for outputting a 1-bit digital signal by performing a delta sigma modulation process on a plurality of input signals, which includes a plurality of integrating unit, a plurality of feedforward arithmetic units that supply an arithmetic result calculated based on an independent feedforward coefficient to each input signal, to each of the plurality of the integrating units, a quantizing unit that quantizes the integrated output outputted from one of the plurality of the integrating unit, a plurality of feedback arithmetic units that supply an arithmetic result obtained by calculating quantized data outputted from the quantizing unit based on the independent feedback coefficient, to each of the plurality of the integrating units, and a mixing unit that mixes the output of the integrating unit of the front stage, the output of the feedforward arithmetic unit and the output of the feedback arithmetic unit and supplies the mixed result to the integrating unit of the rear stage.
摘要翻译： 本发明提供了一种数字信号处理装置，其可以在将重新量化仅一次的情况下将不同滤波器的频率特性混合到多个输入信号中进行混合和增益控制等的批量处理 。 本发明提供了一种数字信号处理装置，用于通过对多个输入信号执行ΔΣ调制处理来输出1位数字信号，该多个输入信号包括多个积分单元，提供算术结果的多个前馈运算单元 基于对每个输入信号的独立的前馈系数计算到所述多个积分单元中的每一个;量化单元，其对从所述多个所述积分单元中的一个输出的积分输出进行量化;多个反馈运算单元， 通过基于独立反馈系数计算从量化单元输出的量化数据到多个积分单元中的每一个获得的算术结果，以及混合单元，其混合前级积分单元的输出， 前馈算术单元和反馈算术单元的输出并提供 混合后果的整合单元。
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5.发明申请公开(公告)号：US20050213669A1
公开(公告)日：2005-09-29
申请号：US11073629
申请日：2005-03-08
申请人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
发明人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
CPC分类号： H04B14/062
摘要： The present invention aims to realize linking of 1-bit signals having respective sampling frequencies that are different from each other and show a relationship of one equal to integer times of the other without noises.
摘要翻译： 本发明旨在实现具有彼此不同的各采样频率的1位信号的链接，并且显示出一个等于另一个无噪声的整数倍的关系。
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公开(公告)号：US07126517B2
公开(公告)日：2006-10-24
申请号：US11151359
申请日：2005-06-14
申请人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
发明人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
IPC分类号： H03M3/00
CPC分类号： H03M3/36 , H03M3/43 , H03M3/45 , H03M3/454 , H03M7/3011 , H03M7/3028 , H03M7/3033 , H03M7/304
摘要： A delta-sigma modulator and delta-sigma modulation method according to the present invention are capable of ensuring a stable 1-bit signal having less distortion at the transition time from an audio signal reproduction state to soundless state while maintaining high sound quality during reproduction of an audio signal representing music or the like, and, at the same time, capable of maintaining high sound quality at the transition time from a soundless state to audio signal reproduction state. The delta-sigma modulator applies delta-sigma modulation to an input signal to output a 1-bit digital signal, and comprises an integration section that applies integration to the input signal, a quantization section that quantizes the integrated output from the integration section, a random noise generation section that generates a random noise signal whose gain has been adjusted based on the integrated output of the integration section, a detection section that detects a predetermined pattern from the input signal, and a changeover section that switches supply and suspension of supply of the random noise signal from the random noise generation section to the quantization section based on a detection result of the detection section.
摘要翻译： 根据本发明的Δ-Σ调制器和Δ-Σ调制方法能够确保在从音频信号再现状态到无声状态的转变时间具有较小失真的稳定的1比特信号，同时在再现期间保持高音质 表示音乐等的音频信号，并且同时能够在从无声状态到音频信号再现状态的转变时保持高音质。 Δ-Σ调制器对输入信号施加Δ-Σ调制以输出1位数字信号，并且包括对输入信号进行积分的积分部分，对来自积分部分的积分输出进行量化的量化部分， 随机噪声生成部，其生成基于积分部的积分输出调整了增益的随机噪声信号;检测部，其根据所述输入信号检测规定图案;以及切换部，切换供给和停止供给 基于检测部的检测结果，从随机噪声生成部到量化部的随机噪声信号。
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公开(公告)号：US07266152B2
公开(公告)日：2007-09-04
申请号：US10629418
申请日：2003-07-29
申请人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
发明人： Masayoshi Noguchi , Gen Ichimura , Nobukazu Suzuki
IPC分类号： H04B14/06
CPC分类号： H03M7/302 , H03M7/3026 , H03M7/3028 , H03M7/3031 , H03M7/304
摘要： A device for performing predetermined processing on an input signal that may have a signal amplitude of more than one bit. The input signal is obtained by subjecting one-bit serial signals to predetermined signal processing, wherein the signal amplitude of more than one bit is converted to a one-bit serial signal by accumulating the signal amplitudes that exceed one bit, delaying the accumulated signal on the basis of the input signal, and outputting the accumulated signal.
摘要翻译： 用于对可能具有多于一位的信号幅度的输入信号执行预定处理的装置。 输入信号是通过对一位串行信号进行预定的信号处理而获得的，其中通过累积超过一位的信号幅度将多于一位的信号幅度转换为1位串行信号，将累积信号延迟 输入信号的基础，并输出累积信号。
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8.发明授权公开(公告)号：US07215262B2
公开(公告)日：2007-05-08
申请号：US11219757
申请日：2005-09-07
申请人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
发明人： Nobukazu Suzuki , Gen Ichimura , Masayoshi Noguchi
CPC分类号： G06F7/602 , H03M7/3028 , H03M7/304
摘要： The present invention provides a digital signal processing apparatus which can perform batch processing of mixing and gain controlling, etc., one time while the frequency characteristics of different filters are being mixed to a plurality of input signals in case of the re-quantization only once. The present invention provides a digital signal processing apparatus for outputting a 1-bit digital signal by performing a delta sigma modulation process on a plurality of input signals, which includes a plurality of integrating unit, a plurality of feedforward arithmetic units that supply an arithmetic result calculated based on an independent feedforward coefficient to each input signal, to each of the plurality of the integrating units, a quantizing unit that quantizes the integrated output outputted from one of the plurality of the integrating unit, a plurality of feedback arithmetic units that supply an arithmetic result obtained by calculating quantized data outputted from the quantizing unit based on the independent feedback coefficient, to each of the plurality of the integrating units, and a mixing unit that mixes the output of the integrating unit of the front stage, the output of the feedforward arithmetic unit and the output of the feedback arithmetic unit and supplies the mixed result to the integrating unit of the rear stage.
摘要翻译： 本发明提供了一种数字信号处理装置，其可以在将重新量化仅一次的情况下将不同滤波器的频率特性混合到多个输入信号中进行混合和增益控制等的批量处理 。 本发明提供了一种数字信号处理装置，用于通过对多个输入信号执行ΔΣ调制处理来输出1位数字信号，该多个输入信号包括多个积分单元，提供算术结果的多个前馈运算单元 基于对每个输入信号的独立的前馈系数计算到所述多个积分单元中的每一个;量化单元，其对从所述多个所述积分单元中的一个输出的积分输出进行量化;多个反馈运算单元， 通过基于独立反馈系数计算从量化单元输出的量化数据到多个积分单元中的每一个获得的算术结果，以及混合单元，其混合前级积分单元的输出， 前馈算术单元和反馈算术单元的输出并提供 混合后果的整合单元。
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公开(公告)号：US07612473B2
公开(公告)日：2009-11-03
申请号：US11475980
申请日：2006-06-28
申请人： Nobukazu Suzuki , Gen Ichimura , Masaru Uryu , Yoshio Ohashi
发明人： Nobukazu Suzuki , Gen Ichimura , Masaru Uryu , Yoshio Ohashi
摘要： A driving device has a magnetostrictive actuator that drives a load member based on a driving signal, a sensor that detects an action of the load member, and a compensation unit that performs feedback compensation on the driving signal which the magnetostrictive actuator receives, based on a detection signal that is received from the sensor.
摘要翻译： 驱动装置具有基于驱动信号驱动负载构件的磁致伸缩致动器，检测负载构件的作用的传感器，以及基于磁致伸缩致动器接收到的驱动信号执行反馈补偿的补偿单元 从传感器接收的检测信号。
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公开(公告)号：US20060276225A1
公开(公告)日：2006-12-07
申请号：US11442968
申请日：2006-05-31
申请人： Nobukazu Suzuki , Gen Ichimura , Masaru Uryu , Yoshio Ohashi
发明人： Nobukazu Suzuki , Gen Ichimura , Masaru Uryu , Yoshio Ohashi
IPC分类号： H04B1/38
CPC分类号： G08B6/00
摘要： An electromechanical transformation device has a magnetostrictive actuator and a driving device that drives the magnetostrictive actuator. The driving device drives the magnetostrictive actuator based on any one of the vibration signal and the audio signal or mixed signal of them.
摘要翻译： 机电转换装置具有磁致伸缩致动器和驱动磁致伸缩致动器的驱动装置。 驱动装置基于振动信号和音频信号中的任何一个或它们的混合信号来驱动磁致伸缩致动器。
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