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公开(公告)号：US20200007141A1
公开(公告)日：2020-01-02
申请号：US16451624
申请日：2019-06-25
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
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公开(公告)号：US10944415B2
公开(公告)日：2021-03-09
申请号：US16451624
申请日：2019-06-25
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
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公开(公告)号：US10673417B2
公开(公告)日：2020-06-02
申请号：US16020283
申请日：2018-06-27
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal.
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公开(公告)号：US11201627B2
公开(公告)日：2021-12-14
申请号：US16548091
申请日：2019-08-22
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
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公开(公告)号：US20200007142A1
公开(公告)日：2020-01-02
申请号：US16548091
申请日：2019-08-22
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
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公开(公告)号：US20200007113A1
公开(公告)日：2020-01-02
申请号：US16020283
申请日：2018-06-27
发明人： Robert J. Murphy
摘要： Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal.
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