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公开(公告)号：US5828245A
公开(公告)日：1998-10-27
申请号：US740129
申请日：1996-10-24
CPC分类号： H03K17/163 , H03K2217/0036
摘要： A driver circuit with an amplifier operated in a switching mode has threshold detectors with devices to compare the amplifier input and output voltage respectively to predetermined minimum and maximum levels representing fully off and fully on conditions for the driver circuit. The circuit provides signals to enable the amplifier to draw current from a supply only during transitions between the threshold levels and to otherwise disable the amplifier. The circuit is beneficial particularly when operating the amplifier from a voltage supply of very limited current capability, such as a charge pump voltage in an integrated circuit. The switching mode amplifier can be applied in high performance driver integrated circuits alone or in combination with innovative techniques for slew rate control and for preslewing the amplifier output that also provide high performance in compact circuit configurations.
摘要翻译： 具有以开关模式操作的放大器的驱动器电路具有阈值检测器，其具有将放大器输入和输出电压分别与驱动器电路的完全关断和完全接通条件的预定最小和最大电平进行比较的装置。 该电路提供信号以使放大器仅在阈值电平之间的转换期间从电源中提取电流，否则禁用放大器。 该电路是有益的，特别是当从具有非常有限的电流能力的电压源（例如集成电路中的电荷泵电压）来操作放大器时。 开关模式放大器可以单独应用于高性能驱动器集成电路，也可以与用于压摆率控制的创新技术结合使用，并且还可以在紧凑型电路配置中提供高性能的放大器输出。
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2.发明授权Driver circuit including slew rate control system with improved voltage ramp generator 失效驱动电路包括具有改进电压斜坡发生器的转换速率控制系统
公开(公告)号：US5825218A
公开(公告)日：1998-10-20
申请号：US736524
申请日：1996-10-24
CPC分类号： H03K17/063 , H03K17/667 , H03K4/94
摘要： A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver. It is optional to have two current sources for charging, also, where a first source with voltage and than a second source, in a basic current mirror, continues charging substantially to the supply voltage.
摘要翻译： 提供用于驱动器电路的电压斜坡发生器，以提供在零之间高度线性的输出，并且最大电压具有用于对电容器充电和放电的电流源或发生器的组合，通过对两种不同类型的电流源 。 在电容器的放电侧的第一电流源具有共源共栅电流镜中的晶体管，并将电容器电压降低到零，但不低于零。 基本或简单的电流镜的第二电流源然后将电容器电压基本上为零。 电压斜坡发生器满足高性能，集成的驱动器电路的要求，特别是为了实现功率器件的完全关断，例如在高侧的DMOS晶体管的共模感应晶体管在全电源驱动器附近达到阈值。 具有两个用于充电的电流源是可选的，而在基本电流镜中，具有电压和第二源的第一源也继续充电至电源电压。
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3.发明授权
公开(公告)号：US5742193A
公开(公告)日：1998-04-21
申请号：US740195
申请日：1996-10-24
CPC分类号： H03K4/00 , H03K17/04123 , H03K17/162 , H03K17/163 , H03K5/12
摘要： A preslewing circuit to rapidly drop a voltage on the gate of a power device in a power stage has a combination of a bipolar transistor and CMOS transistors. The gate voltage is brought down by the preslewing circuit to a level at which an output voltage can begin to change. The combination has high conduction and can be integrated readily, with good internal isolation, in a small chip area, thus having qualities desirable for high performance, integrated, driver circuits.
摘要翻译： 在功率级的功率器件的栅极上快速降低电压的预制电路具有双极晶体管和CMOS晶体管的组合。 栅极电压由预置电路降低到输出电压可以开始变化的水平。 该组合具有高导通性，并且可以在小的芯片面积中容易地集成，具有良好的内部隔离，因此具有高性能，集成的驱动器电路所需的质量。
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公开(公告)号：US06269352B1
公开(公告)日：2001-07-31
申请号：US09461674
申请日：1999-12-14
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
IPC分类号： G06F1518
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译： 包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。 累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。 突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。
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公开(公告)号：USRE41658E1
公开(公告)日：2010-09-07
申请号：US10631323
申请日：2003-07-31
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译： 包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。 累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。 突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。
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公开(公告)号：US6032140A
公开(公告)日：2000-02-29
申请号：US731426
申请日：1996-10-15
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译： 包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。 累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。 突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。
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7.发明授权Low-power, low-voltage four-quadrant analog multiplier, particularly for neural applications 失效低功耗，低电压四象限模拟乘法器，特别适用于神经应用
公开(公告)号：US5805007A
公开(公告)日：1998-09-08
申请号：US721870
申请日：1996-09-27
申请人： Gianluca Colli
发明人： Gianluca Colli
CPC分类号： G06G7/163
摘要： A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.
摘要翻译： 具有四个相乘分支的乘法器，每个分支由缓冲晶体管和由彼此串联布置并连接在两个输出节点和公共节点之间的两个输入晶体管组成。 偏置分支呈现二极管连接的强制晶体管，其栅极端子连接到所有缓冲晶体管的栅极端子，其源极端子连接到公共节点。 强制晶体管迫使输入晶体管在三极管（线性）区域（即，作为压控电阻器）中工作，使得它们导通与各个源极和栅极端子之间的电压降成线性比例的电流，以及通过 输出节点与施加到输入晶体管的控制端的输入电压成比例。 通过将乘法分支交叉耦合到输出节点并减去两个输出电流，获得与两个输入电压的乘积成比例的电流。
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公开(公告)号：US5587682A
公开(公告)日：1996-12-24
申请号：US413772
申请日：1995-03-30
CPC分类号： G06G7/163
摘要： An analog multiplier circuit includes three transconductance stages. One of the transconductance stages, receiving a first differential voltage, conducts a differential current responsive to the first differential voltage from the other two transconductance stages. The differential current changes the transconductance in the other two transconductance stages, which are cross-coupled with one another. The second differential input voltage is presented to the other two transconductance stages in parallel, resulting in an output differential current or voltage based on the product of the first and second differential input voltages. Each of the transconductance stages is implemented in BiCMOS, and each includes two differential legs, each having a MOS transistor receiving an input signal and a cascode bipolar transistor. Each transconductance stage also includes a reference leg which develops the drain-source voltage for the MOS transistors; the first transconductance stage differentially varies this drain-source voltage in the other two stages to produce the product.
摘要翻译： 模拟乘法器电路包括三个跨导级。 接收第一差分电压的跨导级中的一个传导响应于来自其它两个跨导级的第一差分电压的差分电流。 差分电流改变了另外两个跨导级的跨导，它们彼此交叉耦合。 第二差分输入电压并联提供给另外两个跨导级，导致基于第一和第二差分输入电压的乘积的输出差分电流或电压。 每个跨导级在BiCMOS中实现，并且每个跨导级包括两个差分支路，每个支路具有接收输入信号的MOS晶体管和共源共栅双极晶体管。 每个跨导级还包括产生MOS晶体管的漏 - 源电压的参考支路; 第一跨导级在其他两个阶段差异地改变该漏极 - 源极电压以产生该产品。
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公开(公告)号：US5978025A
公开(公告)日：1999-11-02
申请号：US754589
申请日：1996-11-20
CPC分类号： H04N5/353 , H04N5/374 , H04N5/3765 , H04N5/378
摘要： An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.
摘要翻译： 集成图像处理系统包括以行和列排列的单元阵列。 每个单元对应于图像的像素，并且包括用于检测其各个像素的发光强度并用于产生值的光敏元件。 第一开关控制从相应的感光元件转移到存储该值的对应的电容器。 第二开关将每个单元并联连接到公共线。 控制电路接收公共线上的每个单元的值，并产生用于调节第一开关的切换时间间隔的信号。
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公开(公告)号：US5963025A
公开(公告)日：1999-10-05
申请号：US994738
申请日：1997-12-19
申请人： Gianluca Colli
发明人： Gianluca Colli
摘要： A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I.sub.bias). The bias current (I.sub.bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4.sub.beta and mirrored again by a factor "c" on the output of DMOS2. The same I.sub.bias is mirrored by a ratio "b" and multiplied by the product of Q5.sub.beta and Q6.sub.beta. The push-pull current operation at the output terminal (416) is obtained by turning on and off switches SW1 (418) and SW2 (420) that are controlled by a clock signal. The voltage regulator (400) further includes an output voltage clamp (424) that keeps control of the V.sub.boost voltage by controlling the amount of bias current (I.sub.bias).
摘要翻译： 具有电荷泵的电压调节器（400）包括产生偏置电流（Ibias）的偏置电流电路（402）。 偏置电流（Ibias）被第一镜像电路（404）镜像，并与增益级Q4beta相乘，并在DMOS2的输出上再次被因子“c”镜像。 相同的Ibias由比例“b”反映，并乘以Q5beta和Q6beta的乘积。 通过接通和断开由时钟信号控制的开关SW1（418）和SW2（420）来获得输出端子（416）处的推挽电流操作。 电压调节器（400）还包括通过控制偏置电流量（Ibias）来保持对Vboost电压的控制的输出电压钳位（424）。
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