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1.发明授权公开(公告)号：US07861206B2
公开(公告)日：2010-12-28
申请号：US11852759
申请日：2007-09-10
IPC分类号： G06F17/50
CPC分类号： G06F1/26 , H02J7/0065 , H04M1/72522 , H04W52/0229
摘要： A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to input multimedia data received from either the multimedia module or the high-speed interface. The output multimedia data is provided to either the multimedia module or the high-speed interface. An on-chip DC-to-DC converter converts a battery voltage into a supply voltage that is coupled to the multimedia module, the high-speed interface, and/or the processing module.
摘要翻译： 片上系统集成电路包括产生渲染输出数据和高速接口的多媒体模块。 响应于从多媒体模块或高速接口接收的输入多媒体数据，处理模块根据多媒体应用的至少一部分生成输出多媒体数据。 输出多媒体数据被提供给多媒体模块或高速接口。 片上DC-DC转换器将电池电压转换成耦合到多媒体模块，高速接口和/或处理模块的电源电压。
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公开(公告)号：US07278119B2
公开(公告)日：2007-10-02
申请号：US10612577
申请日：2003-07-02
IPC分类号： G06F17/50
CPC分类号： G06F1/26 , H02J7/0065 , H04M1/72522 , H04W52/0229
摘要： A battery-optimized system-on-a-chip includes multimedia module, a high-speed interface, a processing module, on-chip memory, and an on-chip DC-to-DC converter. The multimedia module operably coupled to produce rendered output data from input data received via the high-speed interface and/or from data stored in the on-chip memory. The high-speed interface is operably coupled to provide data to and from an external source. The on-chip memory is operably coupled to store at least a portion of a multimedia application, wherein the processing module processes input multimedia data in accordance with the multimedia application to produce output multimedia data. The on-chip DC-to-DC converter is operably coupled to convert a battery voltage into a supply voltage that is provided to the multimedia module, the high-speed interface, the processing module, and/or the on-chip memory.
摘要翻译： 电池优化的片上系统包括多媒体模块，高速接口，处理模块，片上存储器和片上DC-DC转换器。 多媒体模块可操作地耦合以从经由高速接口接收的输入数据和/或从存储在片上存储器中的数据产生渲染的输出数据。 高速接口可操作地耦合以向外部源提供数据。 片上存储器可操作地耦合以存储多媒体应用的至少一部分，其中处理模块根据多媒体应用处理输入多媒体数据以产生输出多媒体数据。 片上DC-DC转换器可操作地耦合以将电池电压转换成提供给多媒体模块，高速接口，处理模块和/或片上存储器的电源电压。
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3.发明授权公开(公告)号：US07555410B2
公开(公告)日：2009-06-30
申请号：US11494798
申请日：2006-07-27
IPC分类号： G01R31/36
CPC分类号： H04N21/4325 , G01K2219/00 , H02J1/08 , H02J7/0031 , H02J7/0063 , H02M2001/009 , H04N21/41407 , H04N21/4223
摘要： A circuit for use by a multifunction handheld device is coupleable to an audio output device, the multifunction handheld device including a color video display device and a host interface that is coupleable to a host device. The circuit includes a processing module and a memory interface, operably coupled to a memory that stores a plurality of digitally formatted files, and that stores operational instructions that cause the processing module to receive a first digitally formatted file of the plurality of digitally formatted files from the host device when coupled to the host device via the host interface and store the first digitally formatted file in the memory, wherein the first digitally formatted file includes a compressed audio file; receive a second digitally formatted file of the plurality of digitally formatted files from a host device when coupled to the host device via a host interface and store the second digitally formatted file in the memory, wherein the second digitally formatted file includes a compressed video file; playback a selected one of the plurality of digitally formatted files, the playback including the generation of an audio output signal for the audio output device, when the first digitally formatted file is selected, and the playback including rendering the selected one of the digitally formatted files for the color video display device, when the second digitally formatted file is selected.
摘要翻译： 由多功能手持设备使用的电路可耦合到音频输出设备，所述多功能手持设备包括可与主机设备耦合的彩色视频显示设备和主机接口。 电路包括处理模块和存储器接口，可操作地耦合到存储多个数字格式的文件的存储器，并且存储操作指令，使得处理模块从多个数字格式的文件中接收第一数字格式的文件， 所述主机设备经由所述主机接口耦合到所述主机设备并将所述第一数字格式的文件存储在所述存储器中，其中所述第一数字格式化文件包括压缩音频文件; 当经由主机接口耦合到所述主机设备时，从所述主机设备接收所述多个数字格式文件的第二数字格式化文件，并将所述第二数字格式文件存储在所述存储器中，其中所述第二数字格式化文件包括压缩视频文件; 播放所选择的多个数字格式的文件中的一个，当选择第一数字格式化的文件时，播放包括产生音频输出设备的音频输出信号，并且播放包括渲染所选择的数字格式的文件之一 对于彩色视频显示设备，当选择第二个数字格式的文件时。
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公开(公告)号：US20070204175A1
公开(公告)日：2007-08-30
申请号：US11507378
申请日：2006-08-21
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processing system includes a processing module and a memory module for storing plurality of data. A controllable power source supplies a source voltage to the memory module in response to a target voltage. A controller module receives a temperature signal and adjusts the target voltage in response to the temperature signal.
摘要翻译： 处理系统包括处理模块和用于存储多个数据的存储器模块。 可控电源响应于目标电压向存储器模块提供源电压。 控制器模块接收温度信号并根据温度信号调节目标电压。
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公开(公告)号：US07953991B2
公开(公告)日：2011-05-31
申请号：US11507378
申请日：2006-08-21
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processing system includes a processing module and a memory module for storing plurality of data. A controllable power source supplies a source voltage to the memory module in response to a target voltage. A controller module receives a temperature signal and adjusts the target voltage in response to the temperature signal.
摘要翻译： 处理系统包括处理模块和用于存储多个数据的存储器模块。 可控电源响应于目标电压向存储器模块提供源电压。 控制器模块接收温度信号并根据温度信号调节目标电压。
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公开(公告)号：US07036029B2
公开(公告)日：2006-04-25
申请号：US10607960
申请日：2003-06-27
申请人： Marcus W. May , Daniel Mulligan
发明人： Marcus W. May , Daniel Mulligan
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： A method for conserving power begins by measuring processing speed of at least a portion of an integrated circuit (IC) to produce measured processing speed. The portion of the IC may be a test circuit, a critical path of the IC, and/or a replica of the critical path of the IC. The processing continues by comparing the measured processing speed with a critical processing speed for the at least a portion of the integrated circuit. The processing then continues by adjusting supply voltage to the integrated circuit to reduce power consumption of the integrated circuit when the measured processing speed compares favorably to the critical processing speed.
摘要翻译： 通过测量集成电路（IC）的至少一部分的处理速度来产生测量的处理速度，开始节省功率的方法。 IC的部分可以是IC的测试电路，关键路径和/或IC的关键路径的副本。 通过将测量的处理速度与集成电路的至少一部分的关键处理速度进行比较，继续处理。 然后通过调整集成电路的电源电压来继续处理，以便当测量的处理速度与临界处理速度相比时，降低集成电路的功耗。
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7.发明授权Method and apparatus for controlling power consumption of an integrated circuit 有权用于控制集成电路的功耗的方法和装置公开(公告)号：US06366522B1
公开(公告)日：2002-04-02
申请号：US09716616
申请日：2000-11-20
申请人： Marcus W. May , Daniel Mulligan
发明人： Marcus W. May , Daniel Mulligan
IPC分类号： G06F126
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for controlling power consumption of an integrated circuit include processing that begins by producing a system clock from a reference clock based on a system clock control signal. The reference clock may be generated from an external crystal oscillator circuit operable to produce a reference clock at a desired frequency. The processing continues by regulating at least one supply from a power source and an inductor based on a power supply control signal. The processing continues by producing the system clock control signal and the power supply control signal based on a processing transfer characteristic of a computational engine and processing requirements associated with processing at least a portion of an application by the computational engine.
摘要翻译： 用于控制集成电路的功耗的方法和装置包括通过基于系统时钟控制信号从参考时钟产生系统时钟开始的处理。 参考时钟可以从外部晶体振荡器电路产生，该外部晶体振荡器可操作以产生所需频率的参考时钟。 该处理通过基于电源控制信号调节来自电源和电感器的至少一个电源来继续。 该处理继续通过基于计算引擎的处理传送特性和与计算引擎处理至少一部分应用程序相关联的处理要求来产生系统时钟控制信号和电源控制信号。
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8.发明申请Automatically disabling input/output signal processing based on the required multimedia format 有权根据所需的多媒体格式自动禁用输入/输出信号处理公开(公告)号：US20080155134A1
公开(公告)日：2008-06-26
申请号：US11643498
申请日：2006-12-21
申请人： Daniel Mulligan , David Baker
发明人： Daniel Mulligan , David Baker
IPC分类号： G06F3/00
CPC分类号： G06F1/3203 , G06F1/325 , G06F1/3287 , Y02D10/171
摘要： A system and method operable to automatically disable input/output signal processing based on the required data format is provided. The need for an input/output module, such as an encoder, required to process input signal having a first data format (i.e. multimedia format) and produce an output signal having a second format (i.e. multimedia format) is determined. When the input/output module is not required to produce the output signal in the second format, the input/output module is disabled.
摘要翻译： 提供一种用于基于所需数据格式自动禁用输入/输出信号处理的系统和方法。 确定需要处理具有第一数据格式（即，多媒体格式）的输入信号并产生具有第二格式（即多媒体格式）的输出信号所需的诸如编码器的输入/输出模块的需要。 当输入/输出模块不需要以第二格式产生输出信号时，输入/输出模块被禁用。
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公开(公告)号：US07250787B2
公开(公告)日：2007-07-31
申请号：US11526839
申请日：2006-09-25
申请人： Daniel Mulligan
发明人： Daniel Mulligan
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： G06F1/1613 , G06F3/16 , G11B20/10527 , G11C7/16 , G11C2207/16
摘要： A digital audio system on a chip includes a plurality of general purpose input/output (GPIO) modules operably coupled to the bus. Each of the plurality of GPIO modules includes a plurality of GPIO cells, wherein a GPIO cell of the plurality of GPIO cells is coupled to a pin of the digital audio SOC. A first GPIO module of the plurality of GPIO modules functions, in a first mode, as an input/output for system management and functions, in a second mode, as an output. A second GPIO module of the plurality of GPIO modules functions, in a first mode, as an I2C input/output, and functions, in a second mode, as an input/output.
摘要翻译： 芯片上的数字音频系统包括可操作地耦合到总线的多个通用输入/输出（GPIO）模块。 多个GPIO模块中的每一个包括多个GPIO单元，其中多个GPIO单元中的GPIO单元耦合到数字音频SOC的引脚。 多个GPIO模块中的第一GPIO模块在第一模式中作为输出的第二模式中的系统管理和功能的输入/输出起作用。 多个GPIO模块的第二GPIO模块在第一模式中作为I输入/输出输入，在第二模式中作为输入/输出起作用。
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公开(公告)号：US20070103345A1
公开(公告)日：2007-05-10
申请号：US11526839
申请日：2006-09-25
申请人： Daniel Mulligan
发明人： Daniel Mulligan
IPC分类号： H03M7/00
CPC分类号： G06F1/1613 , G06F3/16 , G11B20/10527 , G11C7/16 , G11C2207/16
摘要： A digital audio system on a chip includes a plurality of general purpose input/output (GPIO) modules operably coupled to the bus. Each of the plurality of GPIO modules includes a plurality of GPIO cells, wherein a GPIO cell of the plurality of GPIO cells is coupled to a pin of the digital audio SOC. A first GPIO module of the plurality of GPIO modules functions, in a first mode, as an input/output for system management and functions, in a second mode, as an output. A second GPIO module of the plurality of GPIO modules functions, in a first mode, as an I2C input/output, and functions, in a second mode, as an input/output.
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