公开(公告)号：US08014533B2

公开(公告)日：2011-09-06

申请号：US11300236

申请日：2005-12-14

Applicant: Matthew D. Felder

Inventor： Matthew D. Felder

IPC: H04R5/00

CPC classification number: H04H60/04 ,  G06F3/162 ,  G10L21/0208 ,  H04B1/1036

Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.

Abstract translation: 音频输出电路包括片上左声道放大器模块，片上中心声道放大器模块和片上右声道放大器模块。 左通道IC引脚可操作地耦合到片上左声道放大器模块的输出。 右通道IC引脚可操作地耦合到片上右声道放大器模块的输出。 中心通道IC引脚可操作地耦合到片上中心通道放大器模块的输出端。 中心通道反馈IC引脚可操作地耦合到片上中心通道放大器模块的输入端以提供反馈回路。 左插孔连接可操作地耦合到左通道IC引脚。 右插孔连接可操作地耦合到右通道IC引脚。 耦合到中心反馈IC引脚的插座返回连接。 电感器具有耦合到插座返回连接的第一节点和耦合到中心通道IC引脚的第二节点。

公开(公告)号：US07861206B2

公开(公告)日：2010-12-28

申请号：US11852759

申请日：2007-09-10

Applicant: Matthew Brady Henson ,  Matthew D. Felder ,  Marcus W. May ,  Daniel Mulligan

Inventor： Matthew Brady Henson ,  Matthew D. Felder ,  Marcus W. May ,  Daniel Mulligan

IPC: G06F17/50

CPC classification number: G06F1/26 ,  H02J7/0065 ,  H04M1/72522 ,  H04W52/0229

Abstract: A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to input multimedia data received from either the multimedia module or the high-speed interface. The output multimedia data is provided to either the multimedia module or the high-speed interface. An on-chip DC-to-DC converter converts a battery voltage into a supply voltage that is coupled to the multimedia module, the high-speed interface, and/or the processing module.

Abstract translation: 片上系统集成电路包括产生渲染输出数据和高速接口的多媒体模块。 响应于从多媒体模块或高速接口接收的输入多媒体数据，处理模块根据多媒体应用的至少一部分生成输出多媒体数据。 输出多媒体数据被提供给多媒体模块或高速接口。 片上DC-DC转换器将电池电压转换成耦合到多媒体模块，高速接口和/或处理模块的电源电压。

公开(公告)号：US20100156390A1

公开(公告)日：2010-06-24

申请号：US12721014

申请日：2010-03-10

Applicant: Matthew D. Felder ,  Michael R. May

Inventor： Matthew D. Felder ,  Michael R. May

IPC: H03H7/00

CPC classification number: H04L27/14 ,  H03F3/189 ,  H03F3/343 ,  H03G3/3068

Abstract: A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.

Abstract translation: 用于信号强度检测的方法开始于将信号的信号强度表示与参考信号的信号强度表示进行比较。 该方法通过调节信号的信号强度表示与参考信号的信号强度表示不利地相比较，信号的信号强度表示和参考信号的信号强度表示中的至少一个直到信号强度 信号的表示与参考信号的信号强度表示相当。 该方法通过基于信号的信号强度表示和参考信号的信号强度的调整来确定信号的信号强度来继续。

公开(公告)号：US07656331B2

公开(公告)日：2010-02-02

申请号：US11796968

申请日：2007-04-30

Applicant: Matthew D. Felder ,  Charles Eric Seaberg

Inventor： Matthew D. Felder ,  Charles Eric Seaberg

IPC: H03M3/00

CPC classification number: H04R5/04 ,  H04R2430/01 ,  H04R2499/11

Abstract: An audio output circuit includes a DAC module, a line out circuit, and a headphone amplifier circuit. The digital to analog conversion (DAC) module is coupled to convert an audio component of digitized multimedia data into an analog audio signal. The line out circuit is coupled to amplify the analog audio signal based on a line out volume setting. The headphone amplifier is coupled to amplify the analog audio signal based on a volume setting to produce an amplified analog audio signal.

Abstract translation: 音频输出电路包括DAC模块，线路输出电路和耳机放大器电路。 数模转换（DAC）模块被耦合以将数字化多媒体数据的音频分量转换为模拟音频信号。 线路输出电路被耦合以基于线路输出音量设置来放大模拟音频信号。 耳机放大器被耦合以基于音量设置放大模拟音频信号以产生放大的模拟音频信号。

公开(公告)号：US07596351B2

公开(公告)日：2009-09-29

申请号：US11415825

申请日：2006-05-02

Applicant: Matthew D. Felder

Inventor： Matthew D. Felder

IPC: H04H20/71 ,  H04H1/18

CPC classification number: G11B31/003 ,  H04H60/27 ,  H04H60/74 ,  H04H2201/13

Abstract: A radio record module includes a radio data system (RDS) decoder module, that decodes a received RDS signal, that has an associated audio signal, into received RDS data. A record module produces a digital data file from the digital audio signal in response to a record signal. A catalog generation module generates catalog data associated with the digital audio file, the catalog data including an RDS parameter of the received RDS data. A memory module stores the digital audio file and the catalog data.

Abstract translation: 无线电记录模块包括无线电数据系统（RDS）解码器模块，其将具有相关音频信号的接收的RDS信号解码为接收的RDS数据。 记录模块响应于记录信号从数字音频信号产生数字数据文件。 目录生成模块生成与数字音频文件相关联的目录数据，目录数据包括所接收的RDS数据的RDS参数。 存储器模块存储数字音频文件和目录数据。

公开(公告)号：US07551017B2

公开(公告)日：2009-06-23

申请号：US11304312

申请日：2005-12-14

Applicant: Matthew D. Felder

Inventor： Matthew D. Felder

IPC: H03L5/00

CPC classification number: H03F3/34

Abstract: A level shifter includes a first level shift module for producing a shifted signal by adjusting a direct current (DC) level of an input signal by a first bias voltage having a first polarity. A second level shift module produces an output signal by adjusting a DC level of the shifted signal by a second bias voltage having a second polarity. The first polarity is opposite to the second polarity and the sum of the first bias voltage and the second bias voltage is a non-zero voltage.

Abstract translation: 电平移位器包括第一电平移位模块，用于通过利用具有第一极性的第一偏置电压来调节输入信号的直流电平（DC）来产生移位信号。 第二电平移位模块通过利用具有第二极性的第二偏置电压来调整移位信号的直流电平来产生输出信号。 第一极性与第二极性相反，并且第一偏置电压和第二偏置电压的和是非零电压。

公开(公告)号：US07164320B2

公开(公告)日：2007-01-16

申请号：US11009110

申请日：2004-12-10

Applicant: Matthew D. Felder ,  Marcus W. May

Inventor： Matthew D. Felder ,  Marcus W. May

IPC: H03F3/04

CPC classification number: G05F1/573

Abstract: A current threshold circuit includes a series impedance, a reference voltage source, and a comparison module. The series impedance couples an output of a current source to a load, wherein impedance of the series impedance is substantially less than impedance of the load. The reference voltage source is operably coupled to produce a reference voltage differential. The comparison module is operably coupled to compare the reference voltage differential with a differential voltage of the series impedance, wherein the comparison module generates an excessive current indication when the differential voltage of the series impedance compares unfavorably to the reference voltage differential.

Abstract translation: 电流阈值电路包括串联阻抗，参考电压源和比较模块。 串联阻抗将电流源的输出耦合到负载，其中串联阻抗的阻抗基本上小于负载的阻抗。 参考电压源可操作地耦合以产生参考电压差。 比较模块可操作地耦合以将参考电压差与串联阻抗的差分电压进行比较，其中当串联阻抗的差分电压与参考电压差不利地相比时，比较模块产生过电流指示。

公开(公告)号：US07030695B2

公开(公告)日：2006-04-18

申请号：US10675115

申请日：2003-09-30

Applicant: Marcus W. May ,  Matthew D. Felder

Inventor： Marcus W. May ,  Matthew D. Felder

IPC: H03F3/45 ,  H03F3/26

CPC classification number: H03F3/45192 ,  H03F2200/513

Abstract: An amplifier circuit uses low threshold voltage devices for mid rail response in low voltage applications, but uses a high threshold voltage device at an output stage of the amplifier to generate an output from the amplifier.

Abstract translation: 放大器电路在低电压应用中使用低阈值电压器件用于中间轨道响应，但是在放大器的输出级使用高阈值电压器件来产生放大器的输出。

公开(公告)号：US06608896B2

公开(公告)日：2003-08-19

申请号：US10021397

申请日：2001-12-07

Applicant: Matthew D. Felder ,  James C. Mason ,  Brian L. Evans

Inventor： Matthew D. Felder ,  James C. Mason ,  Brian L. Evans

IPC: H04M300

CPC classification number: H04M7/1295 ,  H04Q1/4575

Abstract: Computationally efficient DTMF detection methods and apparatus are presented that meet all of the ITU recommendations using the modified non-uniform DFT. The system of the present invention employs a high band filter block and two low band filter blocks to detect power at the 8 DTMF tones. The frame length of the high band filter blocks is one half the length of the low band filter blocks. The frame lengths are chosen to meet the ITU frequency selectivity requirements for all DTMF frequencies. The frames of the two low band filter blocks are staggered to produce outputs alternately, and are aligned with respect to the frame of the high band filter block to produce low band filter block outputs that coincided with the high band filter block outputs without the need for signal buffering. A system of power level tests are employed in conjunction with a system of timing tests to ensure that all ITU timing and frequency constraints are met. The present invention requires no buffering of input samples, and can perform DTMF decoding of 24 telephone channels of a T1 time-division multiplexed communication line, using a single fixed-point commercially available digital signal processor.

Abstract translation: 提出了使用改进的非均匀DFT来满足国际电联所有ITU建议的计算高效DTMF检测方法和装置。 本发明的系统采用高频带滤波器模块和两个低频带滤波器块来检测8个DTMF​​音调的功率。 高频带滤波器块的帧长度是低频带滤波器块的长度的一半。 选择帧长度以满足所有DTMF频率的ITU频率选择性要求。 两个低频带滤波器块的帧被交错以交替地产生输出，并且相对于高频带滤波器块的帧被对准以产生与高频带滤波器块输出一致的低频带滤波器块输出，而不需要 信号缓冲。 功率电平测试系统与定时测试系统一起使用，以确保满足所有ITU定时和频率限制。 本发明不需要输入采样的缓冲，并且可以使用单个定点市售的数字信号处理器对T1时分复用通信线路的24个电话信道进行DTMF解码。

公开(公告)号：US06370244B1

公开(公告)日：2002-04-09

申请号：US09054872

申请日：1998-04-03

Applicant: Matthew D. Felder ,  James C. Mason ,  Brian L. Evans

Inventor： Matthew D. Felder ,  James C. Mason ,  Brian L. Evans

IPC: H04M300

CPC classification number: H04M7/1295 ,  H04Q1/4575

Abstract: Computationally efficient DTMF detection methods and apparatus are presented that meet all of the ITU recommendations using the modified non-uniform DFT. The system of the present invention employs a high band filter block and two low band filter blocks to detect power at the 8 DTMF tones. The frame length of the high band filter blocks is one half the length of the low band filter blocks. The frame lengths are chosen to meet the ITU frequency selectivity requirements for all DTMF frequencies. The frames of the two low band filter blocks are staggered to produce outputs alternately, and are aligned with respect to the frame of the high band filter block to produce low band filter block outputs that coincided with the high band filter block outputs without the need for signal buffering. A system of power level tests are employed in conjunction with a system of timing tests to ensure that all ITU timing and frequency constraints are met. The present invention requires no buffering of input samples, and can perform DTMF decoding of 24 telephone channels of a T1 time-division multiplexed communication line, using a single fixed-point commercially available digital signal processor.