公开(公告)号：US5297151A

公开(公告)日：1994-03-22

申请号：US900706

申请日：1992-06-17

申请人： Matthias Gruetzner ,  Leendert M. Huisman ,  Sandip Kundu ,  Cordt W. Starke

发明人： Matthias Gruetzner ,  Leendert M. Huisman ,  Sandip Kundu ,  Cordt W. Starke

IPC分类号： G01R31/3183 ,  G01R31/3181 ,  G06F7/58 ,  G01R31/28

CPC分类号： G01R31/31813 ,  G01R31/318385 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/583

摘要： A test pattern generator includes a random pattern generator and a shift register. The random pattern generator generates a series of digits which are input to the shift register and stored therein. Each digit output by the random pattern generator has a probability of having a first value, such as representing "1". The output probability of the random pattern generator is adjustable. The shift register has a plurality of outputs for outputting a test pattern comprising the stored digits. The shift register includes a series of latches and at least a first logic circuit connecting the output of the random pattern generator to the input of a first latch, or connecting the output of a latch to the input of a next adjacent latch. In a first state, the logic circuit has an output probability which is independent of the output probability of the random pattern generator. In a second state, the logic circuit has an output probability which is dependent on the output probability of the random pattern generator.

摘要翻译： 测试码型发生器包括随机码型发生器和移位寄存器。 随机模式发生器产生一系列数字，输入到移位寄存器并存储在其中。 由随机模式发生器输出的每个数字具有诸如表示“1”的第一值的概率。 随机图案发生器的输出概率是可调整的。 移位寄存器具有多个输出，用于输出包括存储数字的测试图案。 移位寄存器包括一系列锁存器和至少第一逻辑电路，其将随机模式发生器的输出连接到第一锁存器的输入端，或者将锁存器的输出连接到下一个相邻锁存器的输入端。 在第一状态下，逻辑电路具有独立于随机模式发生器的输出概率的输出概率。 在第二状态下，逻辑电路具有取决于随机模式发生器的输出概率的输出概率。

公开(公告)号：US5444715A

公开(公告)日：1995-08-22

申请号：US69466

申请日：1993-06-01

申请人： Matthias Gruetzner ,  Cordt W. Starke

发明人： Matthias Gruetzner ,  Cordt W. Starke

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/31855 ,  G01R31/318577

摘要： An integrated circuit chip (110) adapted to provide interconnect capability and an AC interconnect test method therefor. Test and control data are scanned in the scan-path of latches (114 and 115) to initialize the AC interconnect test. Subsequently the functional system mode is simulated by applying the functional-system clocks via lines (118 and 128).

摘要翻译： 适用于提供互连能力的集成电路芯片（110）及其互连测试方法。 在锁存器（114和115）的扫描路径中扫描测试和控制数据，以初始化AC互连测试。 随后，通过经由线路（118和128）应用功能系统时钟来模拟功能系统模式。

公开(公告)号：US5239262A

公开(公告)日：1993-08-24

申请号：US839418

申请日：1992-02-21

申请人： Matthias Grutzner ,  Cordt W. Starke

发明人： Matthias Grutzner ,  Cordt W. Starke

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F11/22 ,  G06F11/27

CPC分类号： G06F11/27

摘要： An integrated circuit chip with built-in self-test for logic fault detection is described which comprises a number of combinational logic circuits and a number of shift register latches. The combinational logic circuits are coupled via the shift register latches and the shift register latches are connected to form test scan paths. Test weights are created and combined with test patterns and are then applied to the test scan paths of the integrated circuit chip. In contrast to the prior art where the test weights are taken out of a weight storage table, the invention generates the test weights with the help of a so-called "finite state machine", i.e. with a circuit which creates a finite number of test weights without storing them. Therefore, no weight storage table or the like is necessary and the whole tester can be incorporated on the chip.