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    Adjustable weighted random test pattern generator for logic circuits
    1.
    发明授权
    Adjustable weighted random test pattern generator for logic circuits 失效
    用于逻辑电路的可调加权随机测试码发生器

    公开(公告)号：US5297151A

    公开(公告)日：1994-03-22

    申请号：US900706

    申请日：1992-06-17

    申请人： Matthias Gruetzner ,  Leendert M. Huisman ,  Sandip Kundu ,  Cordt W. Starke

    发明人： Matthias Gruetzner ,  Leendert M. Huisman ,  Sandip Kundu ,  Cordt W. Starke

    IPC分类号： G01R31/3183 ,  G01R31/3181 ,  G06F7/58 ,  G01R31/28

    CPC分类号： G01R31/31813 ,  G01R31/318385 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/583

    摘要： A test pattern generator includes a random pattern generator and a shift register. The random pattern generator generates a series of digits which are input to the shift register and stored therein. Each digit output by the random pattern generator has a probability of having a first value, such as representing "1". The output probability of the random pattern generator is adjustable. The shift register has a plurality of outputs for outputting a test pattern comprising the stored digits. The shift register includes a series of latches and at least a first logic circuit connecting the output of the random pattern generator to the input of a first latch, or connecting the output of a latch to the input of a next adjacent latch. In a first state, the logic circuit has an output probability which is independent of the output probability of the random pattern generator. In a second state, the logic circuit has an output probability which is dependent on the output probability of the random pattern generator.

    摘要翻译： 测试码型发生器包括随机码型发生器和移位寄存器。 随机模式发生器产生一系列数字，输入到移位寄存器并存储在其中。 由随机模式发生器输出的每个数字具有诸如表示“1”的第一值的概率。 随机图案发生器的输出概率是可调整的。 移位寄存器具有多个输出，用于输出包括存储数字的测试图案。 移位寄存器包括一系列锁存器和至少第一逻辑电路，其将随机模式发生器的输出连接到第一锁存器的输入端，或者将锁存器的输出连接到下一个相邻锁存器的输入端。 在第一状态下，逻辑电路具有独立于随机模式发生器的输出概率的输出概率。 在第二状态下，逻辑电路具有取决于随机模式发生器的输出概率的输出概率。

    Segmented scan chains with dynamic reconfigurations
    2.
    发明授权
    Segmented scan chains with dynamic reconfigurations 失效
    具有动态重新配置的分段扫描链

    公开(公告)号：US07139950B2

    公开(公告)日：2006-11-21

    申请号：US10707957

    申请日：2004-01-28

    申请人： Leendert M. Huisman ,  Leah M. P. Pastel

    发明人： Leendert M. Huisman ,  Leah M. P. Pastel

    IPC分类号： G01R31/28 ,  G06F17/50

    CPC分类号： G01R31/318536

    摘要： A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially extending segments. A plurality of multiplexors are positioned between the plurality of segments of each scan chain, and are controlled and utilized to connect each segment of the scan chain to the next serial segment in the same scan chain, or to connect each segment of the scan chain to the next serial segment in a lateral adjacent scan chain. Scan in data patterns are introduced into the plurality of serially extending scan chains. Particular defective segments of the plurality of serially extending scan chains are identified by controlling the multiplexors to connect and shift the data pattern out of each segment of a scan chain serially to the next serial segment in the same scan chain, or to connect and shift the data pattern out of each segment of the scan chain to the next serial segment in an adjacent lateral scan chain, with a sequence of serial shifts and serial-lateral shifts being selected to identify particular defective segments of the plurality of serially extending scan chains.

    摘要翻译： 公开了通过静态和动态地分割和重新配置扫描链来诊断扫描链中的缺陷的方法。 多个串联延伸的扫描链被分割成多个串联布置的等长段，使得每个连续延伸的扫描链包括多个串联延伸段。 多个多路复用器位于每个扫描链的多个段之间，并且被控制并用于将扫描链的每个段连接到相同扫描链中的下一个串行段，或将扫描链的每个段连接到 横向相邻扫描链中的下一个串行段。 扫描数据模式被引入到多个连续延伸的扫描链中。 通过控制多路复用器将扫描链的每个段中的数据模式串联连接并移动到同一扫描链中的下一个串行段来识别多个串行延伸扫描链中的特定缺陷段，或者将数据模式连接和移位 扫描链的每个段中的数据模式到相邻横向扫描链中的下一个串行段，其中选择串行移位和串行 - 横向移位序列以识别多个连续延伸扫描链中的特定缺陷段。

    Defect diagnosis for semiconductor integrated circuits
    3.
    发明授权
    Defect diagnosis for semiconductor integrated circuits 失效
    半导体集成电路缺陷诊断

    公开(公告)号：US07089514B2

    公开(公告)日：2006-08-08

    申请号：US10710879

    申请日：2004-08-10

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31718 ,  G01R31/318342

    摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

    摘要翻译： 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

    Methods and apparatus for testing a scan chain to isolate defects
    4.
    发明授权
    Methods and apparatus for testing a scan chain to isolate defects 失效
    用于测试扫描链以隔离缺陷的方法和装置

    公开(公告)号：US07752514B2

    公开(公告)日：2010-07-06

    申请号：US11924597

    申请日：2007-10-25

    申请人： Leendert M. Huisman ,  William V. Huott ,  Maroun Kassab ,  Franco Motika

    发明人： Leendert M. Huisman ,  William V. Huott ,  Maroun Kassab ,  Franco Motika

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318533

    摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

    摘要翻译： 提供了用于隔离扫描链中的缺陷的系统，方法和装置。 本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。 扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值， 到了错误。 这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。 提供了许多其他方面。

    Rapid fail analysis of embedded objects
    6.
    发明授权
    Rapid fail analysis of embedded objects 失效
    嵌入式对象的快速故障分析

    公开(公告)号：US06931580B1

    公开(公告)日：2005-08-16

    申请号：US09524254

    申请日：2000-03-13

    申请人： Kevin J. Barcomb ,  Leendert M. Huisman ,  Mark F. Olive ,  Kevin C. Quandt

    发明人： Kevin J. Barcomb ,  Leendert M. Huisman ,  Mark F. Olive ,  Kevin C. Quandt

    IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C29/56

    CPC分类号： G11C29/006 ,  G11C29/56 ,  G11C29/56008 ,  G11C2029/0401

    摘要： A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.

    摘要翻译： 提供了用于分析IC或晶片上的对象的测试数据的方法。 测试数据链接到有关被测对象的可用布局信息。 某些对象是根据测试数据进行选择的。 所选对象的表示被放置在IC的地图上或晶片的地图上。 该表示应对应于IC或晶片上物体的物理位置。 优选地，该表示包括包围构成对象的所有设备的一个或多个多边形。

    Determination of testability of combined logic end memory by ignoring memory
    7.
    发明授权
    Determination of testability of combined logic end memory by ignoring memory 失效
    通过忽略内存来确定组合逻辑终端内存的可测试性

    公开(公告)号：US4726023A

    公开(公告)日：1988-02-16

    申请号：US862950

    申请日：1986-05-14

    申请人： John L. Carter ,  Leendert M. Huisman ,  Thomas W. Williams

    发明人： John L. Carter ,  Leendert M. Huisman ,  Thomas W. Williams

    IPC分类号： G06F11/26 ,  G11C29/54 ,  G01R31/28

    CPC分类号： G06F11/26 ,  G11C29/54

    摘要： A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.

    摘要翻译： 从上方和下方界定揭示具有嵌入式存储器的集成电路的逻辑部分中的故障的概率的方法。 电路必须按照一组规定设计。 然后针对已删除存储器部分的修改系统计算出一个或多个故障曝光概率，其输入直接连接到其输出。 这种概率可以通过提供的关系与未修改系统中的故障暴露的上限和下限相关联。 这些关系依赖于逻辑部分如何处理给定的测试向量来控制未移动的存储器部分。

    Designing scan chains with specific parameter sensitivities to identify process defects
    10.
    发明授权
    Designing scan chains with specific parameter sensitivities to identify process defects 失效
    设计具有特定参数灵敏度的扫描链，以识别过程缺陷

    公开(公告)号：US07194706B2

    公开(公告)日：2007-03-20

    申请号：US10710642

    申请日：2004-07-27

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

    摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。