公开(公告)号：US07183188B2

公开(公告)日：2007-02-27

申请号：US11033471

申请日：2005-01-12

申请人： Matthias Krönke ,  Joachim Patzer

发明人： Matthias Krönke ,  Joachim Patzer

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858

摘要： The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling an interspace between the electronic circuit units (102a, 102b); an insulation layer (104) being deposited on the electronic circuit units (102a, 102b) and on the intermediate layer (103); a masking layer (105) being deposited on the insulation layer (104); and the masking layer (105) being patterned with a through-plating structure (106); b) patterning a contact-making region by means of the masking layer (105), a contact-making hole (112) being etched through the insulation layer (104) and the intermediate layer (103) as far as the substrate (101), a section of the substrate (101) being uncovered in accordance with the through-plating structure (106); c) filling the contact-making hole (112) with a through-plating material (108); d) polishing back the covering layer (107) deposited on the masking layer (105) as far as the masking layer (105); e) depositing a contact-making layer (109) on the masking layer (105) and the through-plating material, the contact-making layer (109) being electrically contact-connected with the through-plating material (108); and f) patterning the contact-making layer (109) together with the residual masking layer (105) in accordance with a structure of a contact-making layer mask (111) applied to the contact-making layer (109) in order to form interconnects as contact-making connections in a metallization plane (M).

摘要翻译： 本发明提供了一种用于制造接触连接的方法，具有以下步骤：a）提供具有布置在其上的电子电路单元（102a，102b）的基板（101），填充中间层 电子电路单元（102a，102b）; 绝缘层（104）沉积在电子电路单元（102a，102b）上和中间层（103）上; 掩蔽层（105）沉积在绝缘层（104）上; 并且所述掩模层（105）用通孔结构（106）图案化; b）通过掩模层（105）图形化接触制造区域，通过绝缘层（104）和中间层（103）蚀刻到基底（101）的接触制造孔（112） 基板（101）的一部分根据贯通电镀结构（106）未覆盖; c）用穿孔材料（108）填充接触孔（112）; d）将沉积在掩蔽层（105）上的覆盖层（107）抛光至掩蔽层（105）; e）在所述掩蔽层（105）和所述通镀材料上沉积接触层（109），所述接触层（109）与所述通镀材料（108）电接触连接; 以及f）根据施加到接触层（109）的接触层掩模（111）的结构，使接触形成层（109）与残留掩模层（105）一起构图，以形成 作为金属化平面（M）中的接触连接。

公开(公告)号：US20060148227A1

公开(公告)日：2006-07-06

申请号：US11115385

申请日：2005-04-27

申请人： Matthias Kronke ,  Joachim Patzer ,  Werner Graf

发明人： Matthias Kronke ,  Joachim Patzer ,  Werner Graf

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10894

摘要： A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.

摘要翻译： 形成二氧化硅层，并且沉积掩模层，然后图案化以在栅极接触周围的区域中的掩模层中产生在逻辑区域中的栅电极轨道上的开口。 围绕逻辑区域中的栅极电极的栅极触点周围没有表面，减少了二氧化硅层。 覆盖栅极电极轨迹的牺牲层被形成并图案化以在接触开口上方形成用于电池阵列区域中相互相邻的栅极电极轨道之间的位线接触和用于衬底接触半导体的接触开口之上的位线接触的牺牲层块 表面，并且栅极接触逻辑区域中的栅极电极轨迹。 在牺牲层块之间形成填充层，去除牺牲层块。 接触开口区域填充有导电材料。

公开(公告)号：US08969190B2

公开(公告)日：2015-03-03

申请号：US13593614

申请日：2012-08-24

申请人： Stephan Kronholz ,  Joachim Patzer

发明人： Stephan Kronholz ,  Joachim Patzer

IPC分类号： H01L21/44

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

摘要翻译： 本文公开了在硅/锗层上形成硅层的各种方法。 在一个实例中，本文公开的方法包括在形成硅/锗材料之后，在半导体衬底上形成硅/锗材料，执行加热过程以将衬底的温度升高到期望的硅形成温度， 并且在基板的温度达到所需的硅形成温度之后，在硅/锗材料上形成硅层。

公开(公告)号：US20140057415A1

公开(公告)日：2014-02-27

申请号：US13593614

申请日：2012-08-24

申请人： Stephan Kronholz ,  Joachim Patzer

发明人： Stephan Kronholz ,  Joachim Patzer

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

摘要翻译： 本文公开了在硅/锗层上形成硅层的各种方法。 在一个实例中，本文公开的方法包括在形成硅/锗材料之后，在半导体衬底上形成硅/锗材料，执行加热过程以将衬底的温度升高到期望的硅形成温度， 并且在基板的温度达到所需的硅形成温度之后，在硅/锗材料上形成硅层。

公开(公告)号：US20050176239A1

公开(公告)日：2005-08-11

申请号：US11033471

申请日：2005-01-12

申请人： Matthias Kronke ,  Joachim Patzer

发明人： Matthias Kronke ,  Joachim Patzer

IPC分类号： H01L21/283 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858

摘要： The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling an interspace between the electronic circuit units (102a, 102b); an insulation layer (104) being deposited on the electronic circuit units (102a, 102b) and on the intermediate layer (103); a masking layer (105) being deposited on the insulation layer (104); and the masking layer (105) being patterned with a through-plating structure (106); b) patterning a contact-making region by means of the masking layer (105), a contact-making hole (112) being etched through the insulation layer (104) and the intermediate layer (103) as far as the substrate (101), a section of the substrate (101) being uncovered in accordance with the through-plating structure (106); c) filling the contact-making hole (112) with a through-plating material (108); d) polishing back the covering layer (107) deposited on the masking layer (105) as far as the masking layer (105); e) depositing a contact-making layer (109) on the masking layer (105) and the through-plating material, the contact-making layer (109) being electrically contact-connected with the through-plating material (108); and f) patterning the contact-making layer (109) together with the residual masking layer (105) in accordance with a structure of a contact-making layer mask (111) applied to the contact-making layer (109) in order to form interconnects as contact-making connections in a metallization plane (M).

摘要翻译： 本发明提供了一种用于制造接触连接的方法，具有以下步骤：a）提供具有布置在其上的电子电路单元（102a，102b）的基板（101），填充中间层 电子电路单元（102a，102b）; 绝缘层（104）沉积在电子电路单元（102a，102b）上和中间层（103）上; 掩蔽层（105）沉积在绝缘层（104）上; 并且所述掩模层（105）用通孔结构（106）图案化; b）通过掩模层（105）图形化接触制造区域，通过绝缘层（104）和中间层（103）蚀刻到基底（101）的接触制造孔（112） 基板（101）的一部分根据贯通电镀结构（106）未覆盖; c）用穿孔材料（108）填充接触孔（112）; d）将沉积在掩蔽层（105）上的覆盖层（107）抛光至掩蔽层（105）; e）在所述掩蔽层（105）和所述通镀材料上沉积接触层（109），所述接触层（109）与所述通镀材料（108）电接触连接; 以及f）根据施加到接触层（109）的接触层掩模（111）的结构，使接触形成层（109）与残留掩模层（105）一起构图，以形成 作为金属化平面（M）中的接触连接。