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公开(公告)号：US06055665A
公开(公告)日：2000-04-25
申请号：US816766
申请日：1997-03-18
申请人： Maurizio Branchetti , Armando Conci , Carla Golla
发明人： Maurizio Branchetti , Armando Conci , Carla Golla
IPC分类号： G06F11/10
CPC分类号： G06F11/1068
摘要： The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device set up as a multi-sector memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by selection circuitry, whenever the device fails an operation test. The use of a Hamming code for error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.
摘要翻译： 本发明涉及一种恢复故障非易失性存储器的方法。 该方法可以应用于设置为多扇区存储器矩阵的电可编程半导体非易失性存储器件，并且包括用于选择存储器的字或单个字节的选择电路。 根据这种方法，无论何时设备操作测试失败，存储器矩阵都由字节寻址，而不是由存储器字进行寻址。 使用汉明码进行错误纠正来纠正由于制造造成的故障，可以将该方法应用于那些未经测试的设备，否则将被视为拒绝。
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公开(公告)号：US5778012A
公开(公告)日：1998-07-07
申请号：US671848
申请日：1996-06-28
CPC分类号： G06F11/1008
摘要： A memory device including first and second memory cell arrays in which are stored respectively user data and error identification and correction data. The memory device also includes first and second decoding means operationally connected to the first and the second memory cell arrays for producing select user data signals and select error identification and correction data signals. The memory device further includes error identification means operationally coupled to the first and the second decoding means. The memory device also comprises error correction means operationally connected to the first and the second decoding means and to the error identification means. Finally the memory device includes a control unit operationally connected to the second decoding means, to the error identification means and to the error correction means to enable the second decoding means and the error correction means if the error identification means detect an error in the select user data signals.
摘要翻译： 一种包括第一和第二存储单元阵列的存储器件，其中分别存储有用户数据和错误识别和校正数据。 存储装置还包括第一和第二解码装置，可操作地连接到第一和第二存储单元阵列，用于产生选择用户数据信号并选择误差识别和校正数据信号。 存储器装置还包括可操作地耦合到第一和第二解码装置的错误识别装置。 存储装置还包括可操作地连接到第一和第二解码装置和错误识别装置的纠错装置。 最后，存储装置包括操作地连接到第二解码装置的控制单元，如果错误识别装置检测到选择用户中的错误，则错误识别装置和错误校正装置启用第二解码装置和纠错装置 数据信号。
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公开(公告)号：US5822259A
公开(公告)日：1998-10-13
申请号：US846755
申请日：1997-04-30
CPC分类号： G11C16/24 , G11C16/0433
摘要： The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the memory element with a reference low voltage power supply. There is provided a precharge network for the conduction terminal of the flash cell and the network incorporates a complementary pair of transistors. The second transistor of the pair is a natural N-channel MOS type. With the UPROM cell is associated a circuit portion for generating a second live output signal to be applied to the control terminal of the second transistor. The circuit portion includes a timing section and a generation section for the second live output signal.
摘要翻译： 本发明涉及一种包含至少一个EPROM或闪存类型的存储元件的冗余UPROM单元，其具有控制端子和要偏置的导通端子，具有连接到存储元件的反相器的寄存器和连接存储器的MOS晶体管 元件与参考低压电源。 提供了用于闪存单元的导通端子的预充电网络，并且网络包含互补的一对晶体管。 该对的第二晶体管是自然的N沟道MOS型。 与UPROM单元相关联的电路部分用于产生要施加到第二晶体管的控制端的第二实时输出信号。 电路部分包括定时部分和用于第二实时输出信号的生成部分。
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4.发明授权Circuit for discharging a negative potential node to ground, including control of the discharge current 有权用于将负电位节点放电到地的电路，包括放电电流的控制公开(公告)号：US06249172B1
公开(公告)日：2001-06-19
申请号：US09275200
申请日：1999-03-24
IPC分类号： H03K1716
CPC分类号： G11C16/30
摘要： Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.
摘要翻译： 用于由电源电压提供的接地电路，包括参考电压，负电位节点，适于将负电位节点与参考电压耦合以响应于控制信号的第一电路。 提供第二电路，适于在第一电路中确定用于放电负电位节点的受控电流的通过。
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公开(公告)号：US6130572A
公开(公告)日：2000-10-10
申请号：US12331
申请日：1998-01-23
CPC分类号： H02M3/073
摘要： A negative charge pump circuit comprises a plurality of charge pump stages connected in series to each other. Each stage has a stage input terminal and a stage output terminal. A first stage has the stage input terminal connected to a reference voltage, a final stage has the stage output terminal operatively connected to an output terminal of the charge pump at which a negative voltage is developed; intermediate stages have the respective stage input terminal connected to the stage output terminal of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage comprises a first N-channel MOSFET with a first electrode connected to the stage input terminal and a second electrode connected to the stage output terminal, a second N-channel MOSFET with a first electrode connected to the stage output terminal and a second electrode connected to a gate electrode of the first N-channel MOSFET, a boost capacitor with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal switching between the reference voltage and a positive voltage supply, and a second capacitor with one terminal connected to the charge pump stage output terminal and a second terminal connected to a respective second digital signal switching between the reference voltage and the voltage supply. A gate electrode of the second N-channel MOSFET is connected, in the first stage, to a third digital signal switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal.
摘要翻译： 负电荷泵电路包括彼此串联连接的多个电荷泵级。 每个阶段都有一个舞台输入终端和舞台输出终端。 第一级具有连接到参考电压的级输入端，最后级具有可操作地连接到电荷泵的输出端处的级输出端，在该输出端产生负电压; 中间级将各级输入端子连接到前一级的级输出端子，并且各级输出端子连接到后级的级输入端子。 每个级包括第一N沟道MOSFET，其第一电极连接到级输入端，第二电极连接到级输出端，第二N沟道MOSFET，第一电极连接到级输出端，第二电极 连接到第一N沟道MOSFET的栅电极，一个升压电容器，一个端子连接到第一N沟道MOSFET的栅电极，第二端由相应的第一数字信号驱动，在参考电压和正极之间切换 以及第二电容器，其中一个端子连接到电荷泵级输出端子，第二电容器连接到在参考电压和电压源之间切换的相应的第二数字信号。 第二N沟道MOSFET的栅电极在第一级连接到在参考电压和电压源之间切换的第三数字信号，而在剩余阶段，第二N沟道MOSFET的栅电极连接 到舞台输入端。
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公开(公告)号：US6151251A
公开(公告)日：2000-11-21
申请号：US295667
申请日：1999-04-21
IPC分类号： G05F3/20 , H01L27/115 , G11C11/34
CPC分类号： H01L27/115 , G05F3/205
摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.
摘要翻译： 一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。 偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端 偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。 该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管， 连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制 输出节点的电压范围。
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公开(公告)号：US06060753A
公开(公告)日：2000-05-09
申请号：US889653
申请日：1997-07-08
IPC分类号： H01L27/092 , H01L29/76
CPC分类号： H01L27/0928
摘要： A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first terminal of the electronic circuit to receive a supply voltage, and a second terminal of the electronic circuit to receive a second reference potential. The transistors are connected together to form an output terminal of the electronic circuit for connection to an external load. The pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate.
摘要翻译： 公开了一种用于集成在半导体衬底上的电子电路的低噪声输出级。 低噪声输出级包括互连CMOS晶体管对，其包括连接在电子电路的第一端子上以接收电源电压的P沟道上拉晶体管和N沟道下拉晶体管，以及第二端子 以接收第二参考电位。 晶体管连接在一起以形成用于连接到外部负载的电子电路的输出端子。 下拉晶体管形成为三阱结构，以防止放电电流从外部负载通过半导体衬底传播。
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公开(公告)号：US06304490B1
公开(公告)日：2001-10-16
申请号：US09675985
申请日：2000-09-29
IPC分类号： G11C1134
CPC分类号： H01L27/115 , G05F3/205
摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.
摘要翻译： 一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。 偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端 偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。 该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管， 连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制 输出节点的电压范围。
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9.发明授权Voltage regulator for single feed voltage memory circuits, and flash type memory in particular 有权单馈电压存储电路的电压调节器，特别是闪存型存储器
公开(公告)号：US6101118A
公开(公告)日：2000-08-08
申请号：US196204
申请日：1998-11-20
摘要： A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.
摘要翻译： 用于存储器电路的电压调节器具有差分级，其具有接收与温度无关的控制电压的非反相输入端; 连接到接地电压基准的反相输入端子; 连接到适于产生升压电压的升压电路的馈电端子; 以及连接到所述电压调节器的输出端子的输出端子，用于从输入电压的比较开始产生输出电压基准。 电压调节器还包括插入差分级的馈电端子和输出端子之间的连接晶体管，连接晶体管是源极跟随器，其具有连接到差分级的输出端子的控制端子，以及连接到 电压调节器的输出端子，以自限制输出端子上的电压的转换。
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公开(公告)号：US06016073A
公开(公告)日：2000-01-18
申请号：US965068
申请日：1997-11-05
IPC分类号： H01L21/8247 , H01L21/8234 , H01L27/088 , H01L29/788 , H01L29/792 , H02M3/07 , G06F1/10
CPC分类号： H02M3/073
摘要： A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.
摘要翻译： 电荷泵包括串联连接在电荷泵的参考电位和输出端之间的多个级。 多个级包括靠近参考电位的第一组级，以及靠近电荷泵输出端的第二组级。 第一组的每个级包括通过晶体管，其中第一和第二端子分别连接到级的输入端和输出端，第一电容器具有连接到级的输出端的第一板和由第一板驱动的第二板 数字信号在参考电压和正电压之间切换。 第二组的每一级包括结二极管，其具有连接到该级的输入的第一电极和连接到该级的输出的第二电极，以及一第二电容器，该第二电容器具有连接到该级的输出的第一电极和 第二板由参考电压和电压源之间的数字信号切换驱动。
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