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Patent Agency Ranking
公开(公告)号：US09760969B2
公开(公告)日：2017-09-12
申请号：US14641449
申请日：2015-03-09
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Shou-Jen Lai , Chia-Hsien Chou , Po-Chun Fan , Yan-Hong Lu , Chih-Chung Cheng , Hung-Yau Lin
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.
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2.发明公开公开(公告)号：US20240333639A1
公开(公告)日：2024-10-03
申请号：US18128215
申请日：2023-03-29
Applicant: MEDIATEK INC.
Inventor： En-Jui Chang , Chih-Chung Cheng
Abstract: A multi-stage interconnection network includes an M-stage plane routing network and an N-stage destination routing network. The M-stage plane routing network routes a data packet received by an input port of the multi-stage interconnection network to a switch plane according to an M-bit entry selected from a plane encoding table, wherein M bits of the M-bit entry control M stages of the M-stage plane routing network, respectively. The N-stage destination routing network routes the data packet from the switch plane to at least one output port of the multi-stage interconnection network according to at least one N-bit entry selected from a destination encoding table, wherein N bits of each of the at least one N-bit entry control N stages of the N-stage destination routing network, respectively. The multi-stage interconnection network employs a non-blocking network topology.
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公开(公告)号：US20170308988A1
公开(公告)日：2017-10-26
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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公开(公告)号：US10282806B2
公开(公告)日：2019-05-07
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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公开(公告)号：US20160267621A1
公开(公告)日：2016-09-15
申请号：US14641449
申请日：2015-03-09
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Shou-Jen Lai , Chia-Hsien Chou , Po-Chun Fan , Yan-Hong Lu , Chih-Chung Cheng , Hung-Yau Lin
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.
Abstract translation: 提供图形处理系统和图形处理方法。 图形处理系统具有收集器，多个时隙，调度器，仲裁器和至少一个算术逻辑单元（ALU）。 收集器被配置为将多个工作项组合成基本波阵面。 每个基本波前都包括配置为执行相同内核代码的工作项。 调度器被配置为将基本波前分配给时隙。 在一个时隙上存在两个以上的基本波前，形成多个宏波前的一个。 仲裁器被配置为选择一个宏波阵面。 ALU被配置为执行至少所选宏波阵面的基本波阵面的工作项，并输出工作项目的执行结果。
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