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1.发明申请公开(公告)号：US20180039324A1
公开(公告)日：2018-02-08
申请号：US15555084
申请日：2015-10-23
Applicant: MEDIATEK INC.
Inventor： Yen-Lin Lee , Ming-Hsien Lee , Tai-Ying Jiang , Mark Shane Peng , Hui-Hsuan Wang , Jia-Horng Shieh , Chun-Yuan Lai , Shin-Pen Chen , Chung-Hua Yu
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , G06F1/3212 , G06F1/3228 , G06F1/324 , G06F1/329 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/174 , Y02D10/24
Abstract: A controller coupled to a plurality of hardware modules is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.
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公开(公告)号：US20170322616A1
公开(公告)日：2017-11-09
申请号：US15148031
申请日：2016-05-06
Applicant: MEDIATEK INC.
Inventor： Kuo-Su Hsiao , Yen-Lin Lee , Shih-Yen Chiu , Jia-Ming Chen , Mark Shane Peng , Ya-Ting Chang
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/206 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/24
Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy. The user-defined CPU hot-plug policy includes conservative policy, aggressive policy, and hot-plug-balanced policy. The user-defined task-migration policy includes performance policy, and task-migration-balanced policy.
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3.发明申请Dual-System Architecture With Fast Recover And Switching Of Operating System 审中-公开双系统架构，快速恢复和切换操作系统公开(公告)号：US20160055031A1
公开(公告)日：2016-02-25
申请号：US14931500
申请日：2015-11-03
Applicant: MediaTek Inc.
Inventor： Li-Chun Tu , Yu-Cheng Hsieh , Chih-Hsiang Hsiao , Yen-Lin Lee
CPC classification number: G06F9/4893 , G06F9/441 , G06F9/4418
Abstract: Examples of a dual-system architecture capable of fast switching between the operating systems are provided. A first operating system may perform one or more operations associated with an apparatus as an active operating system of the apparatus. The active operating system may be switched from the first operating system to a second operating system for the second operating system to perform a task responsive to a determination that the second operating system is required to perform the task.
Abstract translation: 提供了能够在操作系统之间快速切换的双系统架构的示例。 第一操作系统可以执行与装置相关联的一个或多个操作作为装置的主动操作系统。 主动操作系统可以从第一操作系统切换到用于第二操作系统的第二操作系统，以响应于确定需要第二操作系统来执行任务来执行任务。
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Patent Agency Ranking
公开(公告)号：US10282806B2
公开(公告)日：2019-05-07
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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公开(公告)号：US10031574B2
公开(公告)日：2018-07-24
申请号：US14845879
申请日：2015-09-04
Applicant: MediaTek Inc.
Inventor： Jih-Ming Hsu , Yen-Lin Lee , Jia-Ming Chen , Shih-Yen Chiu , Chung-Ho Chang , Ya-Ting Chang , Ming-Hsien Lee
IPC: G06F1/32
Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.
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公开(公告)号：US20170023997A1
公开(公告)日：2017-01-26
申请号：US15071780
申请日：2016-03-16
Applicant: MediaTek Inc.
Inventor： Jia-Ming Chen , Hung-Lin Chou , Pi-Cheng Hsiao , Yen-Lin Lee , Ya-Ting Chang , Jih-Ming Hsu
CPC classification number: G06F1/3234 , G06F1/263 , G06F1/3206 , G06F1/3287 , G06F9/5094 , Y02D10/171
Abstract: A switch interconnect is dynamically controlled at runtime to connect power sources to processing units in a multiprocessor system. Each power source is shareable by the processing units and each processing unit has a required voltage for processing a workload. When a system condition is detected at runtime, the switch interconnect is controlled to change a connection between at least one processing unit and a shared power source to maximize power efficiency. The shared power source is one of the power sources that supports multiple processing units having different required voltages.
Abstract translation: 交换机互连在运行时动态控制，以将电源连接到多处理器系统中的处理单元。 每个电源可由处理单元共享，并且每个处理单元具有用于处理工作负载的所需电压。 当在运行时检测到系统条件时，控制开关互连以改变至少一个处理单元和共享电源之间的连接以最大化功率效率。 共享电源是支持具有不同所需电压的多个处理单元的电源之一。
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公开(公告)号：US10345887B2
公开(公告)日：2019-07-09
申请号：US15148031
申请日：2016-05-06
Applicant: MEDIATEK INC.
Inventor： Kuo-SU Hsiao , Yen-Lin Lee , Shih-Yen Chiu , Jia-Ming Chen , Mark Shane Peng , Ya-Ting Chang
IPC: G06F1/32 , G06F1/3287 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F1/20 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3293
Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy. The user-defined CPU hot-plug policy includes conservative policy, aggressive policy, and hot-plug-balanced policy. The user-defined task-migration policy includes performance policy, and task-migration-balanced policy.
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公开(公告)号：US20170308988A1
公开(公告)日：2017-10-26
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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