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公开(公告)号：US20240103602A1
公开(公告)日：2024-03-28
申请号：US18134541
申请日：2023-04-13
Applicant: MEDIATEK INC.
Inventor： Ming-Yu Chen , Yen-Hsiang Li
IPC: G06F1/3296
CPC classification number: G06F1/3296
Abstract: A power consumption control device applied to an electronic device includes an image signal processor (ISP), a storage device, a processing circuit, and a control circuit. The ISP is arranged to receive an image signal captured by a camera of the electronic device, and process the image signal to generate a processed image signal. The storage device is arranged to store at least one predetermined image class. The processing circuit is arranged to analyze the processed image signal to detect whether the processed image signal belongs to the at least one predetermined image class to generate a control signal. The control circuit is arranged to switch a mode of the electronic device to a first mode or a second mode according to the control signal, wherein power consumption and performance of the electronic device in the first mode are lower than that in the second mode.
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公开(公告)号：US20170308988A1
公开(公告)日：2017-10-26
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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公开(公告)号：US12253902B2
公开(公告)日：2025-03-18
申请号：US18134541
申请日：2023-04-13
Applicant: MEDIATEK INC.
Inventor： Ming-Yu Chen , Yen-Hsiang Li
IPC: G06F1/32 , G06F1/3296
Abstract: A power consumption control device applied to an electronic device includes an image signal processor (ISP), a storage device, a processing circuit, and a control circuit. The ISP is arranged to receive an image signal captured by a camera of the electronic device, and process the image signal to generate a processed image signal. The storage device is arranged to store at least one predetermined image class. The processing circuit is arranged to analyze the processed image signal to detect whether the processed image signal belongs to the at least one predetermined image class to generate a control signal. The control circuit is arranged to switch a mode of the electronic device to a first mode or a second mode according to the control signal, wherein power consumption and performance of the electronic device in the first mode are lower than that in the second mode.
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公开(公告)号：US10282806B2
公开(公告)日：2019-05-07
申请号：US15134279
申请日：2016-04-20
Applicant: MediaTek Inc.
Inventor： Yen-Hsiang Li , Jih-Ming Hsu , Yen-Lin Lee , Chih-Yu Chang , Chiung-Fu Chen , Chih-Chung Cheng , Chung-Min Kao , Che-Ming Hsu
Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.
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