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公开(公告)号：US10075180B2
公开(公告)日：2018-09-11
申请号：US15809476
申请日：2017-11-10
Applicant: MediaTek Inc.
Inventor： Tao He , Michael A. Ashburn, Jr.
Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.
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公开(公告)号：US20180212618A1
公开(公告)日：2018-07-26
申请号：US15875931
申请日：2018-01-19
Applicant: MediaTek Inc.
Inventor： Tao He , Michael A. Ashburn, JR.
IPC: H03M3/00
Abstract: Circuits for compensating delta-sigma modulators for excess loop delay are described. These circuits may be coupled to quantizers, and may configured to select the threshold values supplied to the quantizers for comparison with an analog signal. The threshold values may each be selected from a corresponding plurality of reference values, and may be set such that the numerical order of threshold values varies over time. For example, the threshold value provided to a first comparator of the quantizer may be greater than the threshold value provided to a second comparator of the quantizer in a first time interval, but the opposite scenario may occur in a second time interval. The circuits may include multiplexers for selecting the threshold values, thermometric encoders, reference selectors and reference multiplexers.
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公开(公告)号：US20180212617A1
公开(公告)日：2018-07-26
申请号：US15809476
申请日：2017-11-10
Applicant: MediaTek Inc.
Inventor： Tao He , Michael A. Ashburn, JR.
IPC: H03M3/00
Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.
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