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公开(公告)号：US10567116B2
公开(公告)日：2020-02-18
申请号：US15995093
申请日：2018-05-31
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Timothy Perrin Fisher-Jeffes , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
IPC: H04L1/00 , H03M13/11 , H04B7/0456 , H03M13/00
Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.
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公开(公告)号：US20180198466A1
公开(公告)日：2018-07-12
申请号：US15862661
申请日：2018-01-05
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Timothy Perrin Fisher-Jeffes , Chong-You Lee , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.
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公开(公告)号：US10790853B2
公开(公告)日：2020-09-29
申请号：US16199216
申请日：2018-11-25
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Cheng-Yi Hsu , Timothy Perrin Fisher-Jeffes , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
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公开(公告)号：US20180331784A1
公开(公告)日：2018-11-15
申请号：US15995093
申请日：2018-05-31
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Timothy Perrin Fisher-Jeffes , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
IPC: H04L1/00 , H03M13/11 , H04B7/0456
CPC classification number: H04L1/0058 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1188 , H03M13/6306 , H03M13/6393 , H03M13/6516 , H04B7/0456 , H04L1/0041 , H04L1/0057 , H04L1/0068
Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.
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公开(公告)号：US20170077968A1
公开(公告)日：2017-03-16
申请号：US14854067
申请日：2015-09-15
Applicant: MEDIATEK Inc.
Inventor： Cheng-Yi Hsu , Mao-Ching Chiu , Wei-Nan Sun
CPC classification number: H04B1/0475 , H04B7/0452 , H04L25/03891 , H04L27/0012
Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.
Abstract translation: 用于干扰消除的装置包括：用于至少接收干扰信号和期望信号的前端处理电路; 内部处理电路，用于信道/噪声估计并用于抑制干扰信号; 以及MIMO（多输入多输出）处理电路，用于基于所抑制的干扰信号盲目地检测干扰信号的干扰参数，并且从所述期望信号共同抵消干扰信号，并基于 检测到的干扰参数和来自内部处理电路的信道/噪声估计。
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Patent Agency Ranking
公开(公告)号：US10608665B2
公开(公告)日：2020-03-31
申请号：US15917260
申请日：2018-03-09
Applicant: MEDIATEK INC.
Inventor： Chong-You Lee , Timothy Perrin Fisher-Jeffes , Maoching Chiu , Wei Jen Chen , Cheng-Yi Hsu , Ju-Ya Chen , Yen Shuo Chang
Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.
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公开(公告)号：US10432227B2
公开(公告)日：2019-10-01
申请号：US15878350
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Wei-Jen Chen , Ju-Ya Chen , Yen-Shuo Chang , Timothy Perrin Fisher-Jeffes , Mao-Ching Chiu , Cheng-Yi Hsu , Chong-You Lee
Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
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公开(公告)号：US20190097657A1
公开(公告)日：2019-03-28
申请号：US16199216
申请日：2018-11-25
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Cheng-Yi Hsu , Timothy Perrin Fisher-Jeffes , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
CPC classification number: H03M13/1168 , H03M13/033 , H03M13/116 , H03M13/616 , H03M13/6306 , H03M13/6516 , H04L1/0057 , H04L1/0068 , H04L1/1819
Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value
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公开(公告)号：US20180227077A1
公开(公告)日：2018-08-09
申请号：US15888733
申请日：2018-02-05
Applicant: MEDIATEK INC.
Inventor： Chong-You LEE , Cheng-Yi Hsu , Maoching Chiu , Timothy Perrin Fisher-Jeffes , Ju-Ya Chen , Yen Shuo Chang , Wei Jen Chen
Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
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公开(公告)号：US20180212628A1
公开(公告)日：2018-07-26
申请号：US15878357
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Ju-Ya Chen , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Mao-Ching Chiu , Timothy Perrin Fisher-Jeffes , Chong-You Lee
CPC classification number: H03M13/2792 , H03M13/1105 , H03M13/116 , H03M13/255 , H03M13/2707 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
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