-
公开(公告)号：US08064239B2
公开(公告)日：2011-11-22
申请号：US12617352
申请日：2009-11-12
IPC分类号： G11C17/00
CPC分类号： G11C11/404 , B82Y10/00 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.
摘要翻译： 数据存储在具有双门控制的量子阱型结构中。 根据示例实施例，基于晶体管的数据存储电路包括栅极，背栅极和栅极与后栅极之间的半导体沟道。 响应于施加到门和后门的偏压，载体存储在通道中的存储袋结构中。 感测通过通道的电流，并用于检测存储的载波，并相应地检测存储电路的存储状态。
-
公开(公告)号：US20100149864A1
公开(公告)日：2010-06-17
申请号：US12617352
申请日：2009-11-12
CPC分类号： G11C11/404 , B82Y10/00 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.
摘要翻译： 数据存储在具有双门控制的量子阱型结构中。 根据示例实施例，基于晶体管的数据存储电路包括栅极，背栅极和栅极与后栅极之间的半导体沟道。 响应于施加到门和后门的偏压，载体存储在通道中的存储袋结构中。 感测通过通道的电流，并用于检测存储的载波，并相应地检测存储电路的存储状态。
-
3.发明授权Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS 有权具有与PMOS和NMOS相同的沟道和势垒结构的异质结场场效应晶体管公开(公告)号：US08933488B2
公开(公告)日：2015-01-13
申请号：US13309316
申请日：2011-12-01
CPC分类号： H01L29/1054 , H01L21/02395 , H01L21/02466 , H01L21/02502 , H01L21/02549 , H01L29/517 , H01L29/66462 , H01L29/802 , H01L2924/10348
摘要： In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
摘要翻译： 根据一个或多个实施例，装置和方法包括沟道区，由沟道区隔开的势垒层和阻挡层中的一个上的电介质。 阻挡层具有与沟道区的带隙不同的带隙，并且限制沟道区中的电子和空穴。 栅电极通过电介质将电场施加到沟道区。 在各种情况下，该装置和方法适用于基于电子和基于空穴的实现，例如针对nmos，pmos和cmos应用的实现。
-
公开(公告)号：US20120138899A1
公开(公告)日：2012-06-07
申请号：US13309316
申请日：2011-12-01
CPC分类号： H01L29/1054 , H01L21/02395 , H01L21/02466 , H01L21/02502 , H01L21/02549 , H01L29/517 , H01L29/66462 , H01L29/802 , H01L2924/10348
摘要： In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
摘要翻译： 根据一个或多个实施例，装置和方法包括沟道区，由沟道区隔开的势垒层和阻挡层中的一个上的电介质。 阻挡层具有与沟道区的带隙不同的带隙，并且限制沟道区中的电子和空穴。 栅电极通过电介质将电场施加到沟道区。 在各种情况下，该装置和方法适用于基于电子和基于空穴的实现，例如针对nmos，pmos和cmos应用的实现。
-
公开(公告)号：US07728387B1
公开(公告)日：2010-06-01
申请号：US11761830
申请日：2007-06-12
IPC分类号： H01L31/119
CPC分类号： H01L29/1054 , H01L29/78
摘要： Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.
摘要翻译： 采用各种半导体器件和制造方法。 根据本发明的示例性实施例，MOS兼容半导体器件表现出高的沟道迁移率和低的泄漏。 该装置包括在应变材料层上具有高迁移率应变材料层和隧道缓解层的沟道区，以减轻隧道泄漏。 应变材料具有应变以匹配隧道缓解层的晶格结构的晶格结构。 绝缘体层位于隧道缓解层上，并且电极在绝缘体上方并且适于向通道区域施加电压偏置，以在导电状态和非导通状态之间切换器件。 电流以导电状态传输，主要通过应变材料层的迁移率促进，并且其中非导电状态的隧穿电流被隧道缓解层减轻。
-
-
-
-
搜索结果
5 条记录 (耗时 0.024 秒)
