公开(公告)号：US6144387A

公开(公告)日：2000-11-07

申请号：US55094

申请日：1998-04-03

申请人： Mei-Chi Liu ,  Adrian Sfarti ,  Adam Malamy ,  Nicholas Baker ,  John Cumming

发明人： Mei-Chi Liu ,  Adrian Sfarti ,  Adam Malamy ,  Nicholas Baker ,  John Cumming

IPC分类号： G06T15/30 ,  G06T15/10

CPC分类号： G06T15/30

摘要： Performing graphics rendering without the computational expense of hither plane clipping and with only a minimum of display image clipping. Where a three dimensional polygon crosses to both sides of a hither plane, any vertices on the back side of the hither plane are translated to the hither plane, producing polygons which occupy only the area in front of the hither plane. A display image memory, from which display images are generated, is located within a larger guard memory such that many images which would need to be clipped to fit in the display image memory may be written to the guard memory without clipping.

摘要翻译： 执行图形渲染，而不需要平面裁剪的计算费用，只有最小的显示图像裁剪。 在三维多边形与两个平面的两侧相交的位置上，任一平面的背面上的任何顶点都被平移到两个平面，产生仅在该平面前面区域的多边形。 生成显示图像的显示图像存储器位于更大的保护存储器内，使得需要被剪切以适合显示图像存储器的许多图像可以被写入保护存储器而不会被削波。

公开(公告)号：US06529207B1

公开(公告)日：2003-03-04

申请号：US09584463

申请日：2000-05-31

申请人： Edouard Landau ,  Adrian Sfarti ,  Adam Malamy ,  Mei-Chi Liu ,  Robert Laker ,  Paolo Sabella

发明人： Edouard Landau ,  Adrian Sfarti ,  Adam Malamy ,  Mei-Chi Liu ,  Robert Laker ,  Paolo Sabella

IPC分类号： G09A500

CPC分类号： G06T15/503

摘要： A graphics rendering system creates an image based on objects constructed of polygonal primitives, which can generate the perception of three-dimensional objects displayed on a two-dimensional display device. An anti-aliasing operation is applied to silhouette edges of the objects, which are the edges of primitives which are displayed at the perimeter of an object. A silhouette edge can be identified by determining how many times an edge is rendered, with each instance of the rendering of an edge corresponding to the rendering of a primitive that adjoins the edge. An edge that is rendered exactly once is interpreted as a silhouette edge. An example of a silhouette edge is an edge that adjoins one triangular primitive that is viewable and another triangular primitive that is hidden from view by other primitives. Another technique for identifying a silhouette edge can be applied to closed objects by determining whether a first primitive adjoining an edge is hidden from view by other primitives and a second primitive also adjoining the edge is viewable. Once the silhouette edges are identified, the anti-aliasing operation is applied thereto.

摘要翻译： 图形渲染系统基于由多边形基元构成的对象创建图像，其可以产生在二维显示设备上显示的三维对象的感知。 反锯齿操作被应用于对象的轮廓边缘，对象的边缘是在对象的周边显示的图元的边缘。 可以通过确定渲染边缘的次数来确定轮廓边缘，每个边缘的渲染实例与邻接边缘的原始图像的渲染相对应。 渲染一次的边被解释为剪影边缘。 剪影边缘的一个例子是毗邻可见的一个三角形原语的边缘，另一个三角形原语被其他图元隐藏。 用于识别轮廓边缘的另一种技术可以通过确定邻接边缘的第一图元是否被其他图元隐藏而不被视图所覆盖，并且还可以看到与边缘相邻的第二图元，将其应用于闭合对象。 一旦确定了轮廓边缘，则对其进行抗混叠操作。

公开(公告)号：US6115050A

公开(公告)日：2000-09-05

申请号：US57327

申请日：1998-04-08

申请人： Edouard Landau ,  Adrian Sfarti ,  Adam Malamy ,  Mei-Chi Liu ,  Robert Laker ,  Paolo Sabella

发明人： Edouard Landau ,  Adrian Sfarti ,  Adam Malamy ,  Mei-Chi Liu ,  Robert Laker ,  Paolo Sabella

IPC分类号： G06T15/50 ,  G06T15/10

CPC分类号： G06T15/503

摘要： A graphics rendering system creates an image based on objects constructed of polygonal primitives. Aliasing effects in the image are reduced by applying an anti-aliasing scheme to the areas of the image representing silhouette edges of the objects. The silhouette edges are anti-aliased by creating anti-aliasing primitives which vary in opacity. These anti-aliasing primitives are joined to the silhouetted edges, and create a region in the image where the objects appear to blend into the background.

摘要翻译： 图形渲染系统基于由多边形原语构造的对象创建图像。 通过在表示对象的轮廓边缘的图像的区域中应用抗锯齿方案来减少图像中的混叠效果。 剪影边缘通过创建不透明度不同的抗锯齿原语来反锯齿。 这些抗锯齿原语被连接到被映射的边缘，并且在图像中创建一个区域，其中对象看起来融合到背景中。

公开(公告)号：US6094201A

公开(公告)日：2000-07-25

申请号：US57393

申请日：1998-04-08

申请人： Adam Malamy ,  Nicholas R. Baker ,  Robert Laker ,  Padma Parthasarathy ,  Adrian Sfarti

发明人： Adam Malamy ,  Nicholas R. Baker ,  Robert Laker ,  Padma Parthasarathy ,  Adrian Sfarti

IPC分类号： G06T15/80 ,  G06T11/20

CPC分类号： G06T15/80

摘要： A system and method of rendering polygons in graphics system using incremental iterative addition in place of complex division operations. A setup engine provides relevant values to edge and span walk modules for rapid processing and rendering of polygon characteristics including material values. Characteristic functions are iterated with respect to polygon area and along individual spans to derive values for each pixel therein.

摘要翻译： 使用增量迭代加法在图形系统中渲染多边形来代替复杂分割操作的系统和方法。 设置引擎为边缘和跨度步行模块提供相关值，用于快速处理和渲染包括材料值在内的多边形特征。 特征函数相对于多边形区域和沿着跨度迭代，以导出其中的每个像素的值。

公开(公告)号：US6100898A

公开(公告)日：2000-08-08

申请号：US57171

申请日：1998-04-08

申请人： Adam Malamy ,  Nicholas R. Baker ,  Adrian Sfarti ,  Victor Tirva

发明人： Adam Malamy ,  Nicholas R. Baker ,  Adrian Sfarti ,  Victor Tirva

IPC分类号： G06T15/04 ,  G06T11/40

CPC分类号： G06T15/04

摘要： A system and method of selecting a level of detail in a texture-mapping system. Pixels are processed in a zig-zag traversal pattern to allow determination of vertical and horizontal change values in texture map coordinates. In this manner, accurate level of detail selection is achieved without unduly reducing efficiency or throughput of the graphics system.

摘要翻译： 在纹理映射系统中选择细节级别的系统和方法。 以Z字形遍历模式处理像素，以便确定纹理贴图坐标中的垂直和水平变化值。 以这种方式，在不会不当地降低图形系统的效率或吞吐量的情况下实现精确的细节选择水平。

公开(公告)号：US06219070B1

公开(公告)日：2001-04-17

申请号：US09164003

申请日：1998-09-30

申请人： Nick Baker ,  Adam Malamy ,  Adrian Sfarti ,  Paul Paternoster ,  Padma Parthasarathy

发明人： Nick Baker ,  Adam Malamy ,  Adrian Sfarti ,  Paul Paternoster ,  Padma Parthasarathy

IPC分类号： G06T1570

CPC分类号： G06T13/00

摘要： A method and system for simulating motion of a polygon on a display screen. The polygon may be included in a set of polygons used to model a three-dimensional object. The position of the polygon is defined by vertices tracked in a subpixel coordinate system existing in a computer-readable medium. The subpixel coordinates of the vertices are used to identify the pixels on the display screen having coordinates that correspond to subpixel coordinates lying within or, optionally, at the boundary of the polygon. The identified pixels are those that are to be lighted on the display screen to generate the image of the polygon. The display properties of the lighted pixels are selected by interpolation based on defined pixel display parameters assigned to the vertices of the triangle. As motion of the polygon is tracked in the subpixel coordinate system, the corresponding display on the display screen is repeatedly adjusted. The method of identifying and interpolating the display parameters of the pixels using the subpixel coordinate system provides the appearance of smooth polygon motion.

摘要翻译： 一种用于模拟多边形在显示屏上的运动的方法和系统。 多边形可以被包括在用于建模三维对象的一组多边形中。 多边形的位置由在计算机可读介质中存在的子像素坐标系中跟踪的顶点定义。 顶点的子像素坐标用于识别具有对应于位于多边形边界内的子像素坐标的坐标的显示屏幕上的像素。 所识别的像素是要在显示屏上点亮以产生多边形图像的像素。 通过基于分配给三角形的顶点的定义的像素显示参数进行插值来选择点亮像素的显示属性。 由于在子像素坐标系中跟踪多边形的运动，所以重复地调节显示屏上的对应显示。 使用子像素坐标系确定和内插像素的显示参数的方法提供平滑多边形运动的出现。

公开(公告)号：US5781721A

公开(公告)日：1998-07-14

申请号：US714515

申请日：1996-09-16

申请人： Norman M. Hayes ,  Adam Malamy ,  Rajiv N. Patel

发明人： Norman M. Hayes ,  Adam Malamy ,  Rajiv N. Patel

IPC分类号： G06F12/08 ,  G01R31/317 ,  G06F12/16 ,  G11C29/10 ,  H01L21/66 ,  G11C29/00

CPC分类号： G01R31/31701 ,  G01R31/31713 ,  G11C29/10

摘要： An apparatus and method for enabling a cache controller and address and data buses of a microprocessor with an on-board cache to provide a SRAM test mode for testing the on-board cache. Upon assertion of a SRAM test signal to a SRAM test pin on the microprocessor chip, the cache and bus controllers cease normal functionality and permit data to be written to, and read from, individual addresses within the on-board cache as though the on-board cache is simple SRAM. After the chip is reset, standard SRAM tests can then be implemented by reading and writing data to selected cache memory addresses as though the cache memory were SRAM. Upon completion of the tests, the SRAM test signal is deasserted and the cache and bus controllers resume normal operating functionality. A reset signal is then applied to the microprocessor to reinitialize control logic employed within the microprocessor. In this way, cache memory on-board a microprocessor can be tested using standard SRAM testing algorithms and equipment thereby eliminating a need for specialized test equipment to test cache memory contained on a microprocessor chip.

摘要翻译： 一种用于使得高速缓存控制器和具有板上高速缓存的微处理器的地址和数据总线能够提供用于测试车载高速缓存的SRAM测试模式的装置和方法。 在将SRAM测试信号断言给微处理器芯片上的SRAM测试引脚之后，高速缓存和总线控制器停止正常的功能，并允许将数据写入板载缓存中的单个地址并从其读取， 板缓存是简单的SRAM。 芯片复位后，可以通过将数据读取和写入选定的高速缓冲存储器地址来实现标准SRAM测试，就好像高速缓存是SRAM一样。 测试完成后，SRAM测试信号被断言，缓存和总线控制器恢复正常的操作功能。 然后将复位信号施加到微处理器以重新初始化微处理器内采用的控制逻辑。 以这种方式，可以使用标准SRAM测试算法和设备来测试微处理器上的高速缓存，从而无需专门的测试设备来测试包含在微处理器芯片上的高速缓冲存储器。

公开(公告)号：US5708792A

公开(公告)日：1998-01-13

申请号：US681602

申请日：1996-07-29

申请人： Norman M. Hayes ,  Adam Malamy

发明人： Norman M. Hayes ,  Adam Malamy

IPC分类号： G06F12/08

CPC分类号： G06F12/0833

摘要： A method and apparatus for maintaining cache coherency in a multiprocessor system having a plurality of processors and a shared main memory. Each of the plurality of processors is coupled to at least one cache unit and a store buffer. The method comprises the steps of writing by a first cache unit to its first store buffer a dirty line when the first cache unit experiences a cache miss; gaining control of the bus by the first cache unit; reading a new line from the share main memory by the first cache unit through the bus; writing the dirty line to the shared main memory if the bus is available to the first cache unit and if not available, the first cache unit checking snooping by a second cache unit from a second processor; comparing an address from the second cache unit with the tag of the dirty line, wherein the tag is stored in content-addressable memory coupled to the store buffer and if there is a hit, then supplying the dirty line to the second cache unit for updating.

摘要翻译： 一种用于在具有多个处理器和共享主存储器的多处理器系统中维持高速缓存一致性的方法和装置。 多个处理器中的每一个耦合到至少一个高速缓存单元和存储缓冲器。 该方法包括以下步骤：当第一高速缓存单元经历高速缓存未命中时，由第一高速缓存单元向其第一存储缓冲区写入脏行; 由第一缓存单元获得对总线的控制; 通过总线从第一缓存单元读取共享主存储器中的新行; 如果总线可用于第一高速缓存单元并且如果不可用，则将脏线写入共享主存储器，第一高速缓存单元通过第二高速缓存单元从第二处理器检测窥探; 将来自第二高速缓存单元的地址与脏线的标签进行比较，其中标签被存储在耦合到存储缓冲器的内容可寻址存储器中，并且如果存在命中，则将脏线提供给第二高速缓存单元以进行更新 。

公开(公告)号：US5537665A

公开(公告)日：1996-07-16

申请号：US518659

申请日：1995-08-24

申请人： Rajiv N. Patel ,  Adam Malamy

发明人： Rajiv N. Patel ,  Adam Malamy

IPC分类号： G06F12/08 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

CPC分类号： G11C29/76

摘要： An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a microprocessor. Upon sensing deassertion of a reset signal, a master controller supplies non-overlapping two phase clock signals to one bank controller for each bank of the cache memory. Each bank has a set of fuses which supply a bank shift location to the bank controller indicating the location of a bad column in the bank. The master controller also activates a pre-loadable counter which provides each bank controller with a signal which counts down to zero from half the maximum number of columns in a bank. Each bank controller then provides the shifting signals necessary to initialize the shifting circuitry for its bank. In this way, defective columns located in different positions in each bank can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

摘要翻译： 一种用于控制移位电路的初始化的装置和方法，其为微处理器上的多组缓存存储器提供列冗余。 在感测到取消复位信号时，主控制器为高速缓冲存储器的每一组提供非重叠的两相时钟信号给一个存储体控制器。 每个银行都有一套保险丝，为银行控制人提供一个银行转账位置，指示银行中一个不良列的位置。 主控制器还激活一个可预加载的计数器，为每个银行控制器提供一个信号，该信号从银行中最大列数的一半倒数为零。 然后，每个银行控制器提供为其银行初始化移位电路所必需的移动信号。 以这种方式，位于每个组中不同位置的缺陷列可以被冗余路径替代，从而修复高速缓存并且通过机载缓存存储器增加微处理器的制造产量。

公开(公告)号：US5353425A

公开(公告)日：1994-10-04

申请号：US875357

申请日：1992-04-29

申请人： Adam Malamy ,  Rajiv N. Patel ,  Norman M. Hayes

发明人： Adam Malamy ,  Rajiv N. Patel ,  Norman M. Hayes

IPC分类号： G06F12/12 ,  G06F13/14

CPC分类号： G06F12/126 ,  G06F12/125

摘要： In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit. By providing that the process controls the state of the lock bits, the intelligence and knowledge the process contains regarding the frequency of use of certain memory locations can be utilized to provide a more efficient cache.

摘要翻译： 在具有主存储器和更快的高速缓冲存储器的存储器系统中，提供具有锁定特征的高速缓存存储器替换方案。 在缓存中与每行相关联的锁定位在标签表中提供。 这些锁定位优选地通过执行应用程序/处理来设置和复位，并且由高速缓存控制器结合高速缓存替换位使用以确定要替换的高速缓存中的行。 高速缓存行的锁定位和替换位为“OR”以创建高速缓存行的复合位。 如果复合位置1，高速缓存行不会从缓存中删除。 当由于所有复合位被置位而导致死锁将导致所有替换位被清除。 一条缓存​​线始终保持不可锁定。 锁定位“锁定”高速缓存中的数据行，直到进程重置锁定位为止。 通过提供该过程控制锁定位的状态，可以利用该过程包含关于某些存储器位置的使用频率的智能和知识来提供更有效的缓存。