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    System and method for adjusting pixel parameters by subpixel positioning
    1.
    发明授权
    System and method for adjusting pixel parameters by subpixel positioning 有权
    通过子像素定位来调整像素参数的系统和方法

    公开(公告)号：US06219070B1

    公开(公告)日：2001-04-17

    申请号：US09164003

    申请日：1998-09-30

    申请人： Nick Baker ,  Adam Malamy ,  Adrian Sfarti ,  Paul Paternoster ,  Padma Parthasarathy

    发明人： Nick Baker ,  Adam Malamy ,  Adrian Sfarti ,  Paul Paternoster ,  Padma Parthasarathy

    IPC分类号： G06T1570

    CPC分类号： G06T13/00

    摘要： A method and system for simulating motion of a polygon on a display screen. The polygon may be included in a set of polygons used to model a three-dimensional object. The position of the polygon is defined by vertices tracked in a subpixel coordinate system existing in a computer-readable medium. The subpixel coordinates of the vertices are used to identify the pixels on the display screen having coordinates that correspond to subpixel coordinates lying within or, optionally, at the boundary of the polygon. The identified pixels are those that are to be lighted on the display screen to generate the image of the polygon. The display properties of the lighted pixels are selected by interpolation based on defined pixel display parameters assigned to the vertices of the triangle. As motion of the polygon is tracked in the subpixel coordinate system, the corresponding display on the display screen is repeatedly adjusted. The method of identifying and interpolating the display parameters of the pixels using the subpixel coordinate system provides the appearance of smooth polygon motion.

    摘要翻译： 一种用于模拟多边形在显示屏上的运动的方法和系统。 多边形可以被包括在用于建模三维对象的一组多边形中。 多边形的位置由在计算机可读介质中存在的子像素坐标系中跟踪的顶点定义。 顶点的子像素坐标用于识别具有对应于位于多边形边界内的子像素坐标的坐标的显示屏幕上的像素。 所识别的像素是要在显示屏上点亮以产生多边形图像的像素。 通过基于分配给三角形的顶点的定义的像素显示参数进行插值来选择点亮像素的显示属性。 由于在子像素坐标系中跟踪多边形的运动，所以重复地调节显示屏上的对应显示。 使用子像素坐标系确定和内插像素的显示参数的方法提供平滑多边形运动的出现。

    Method and apparatus for reducing checking costs in fault tolerant processors
    4.
    发明授权
    Method and apparatus for reducing checking costs in fault tolerant processors 失效
    降低容错处理器检查成本的方法和装置

    公开(公告)号：US5339408A

    公开(公告)日：1994-08-16

    申请号：US998715

    申请日：1992-12-30

    申请人： William Bruckert ,  Thomas D. Bissett ,  Glenn Dearth ,  Paul Paternoster

    发明人： William Bruckert ,  Thomas D. Bissett ,  Glenn Dearth ,  Paul Paternoster

    IPC分类号： G06F1/12 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089

    CPC分类号： G06F1/12 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1683 ,  G06F13/28 ,  G06F13/4243 ,  H03L7/085 ,  H03L7/087 ,  G06F11/006 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1654 ,  G06F11/20 ,  G06F11/2205 ,  H03D13/003 ,  H03L7/089

    摘要： According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

    摘要翻译： 根据本发明的一个方面，一种装置包括耦合到第一系统总线以向高速缓存和存储器提供数据的第一处理器，以及耦合到第一系统总线的第二处理器和用于接收读取数据的第二缩写系统总线 从第一个系统总线。 根据本发明的另一方面，一种装置包括用于校正存储器中的错误的装置。 根据本发明的另一方面，一种装置包括多个计算系统，每个计算系统包括安装在不经常更换的硬件单元上并且能够与多个计算系统进行通信的存储器装置。 根据本发明的另一方面，一种装置包括计数器，用于检测所述计数器的选定状态的装置，以及响应于来自所述计数器的输出信号的装置，用于选择性地允许或禁止馈送到循环状态装置的数据的传送 。 根据本发明的另一方面，一种装置包括用于提供第一时钟信号的第一装置，用于提供第二时钟信号的第二装置，用于响应于第一和第二时钟信号的边缘之间的偏移而提供误差信号的装置 时钟信号。

    Connection between an I/O region and the core region of an integrated circuit
    5.
    发明申请
    Connection between an I/O region and the core region of an integrated circuit 有权
    I / O区域与集成电路的核心区域之间的连接

    公开(公告)号：US20080164615A1

    公开(公告)日：2008-07-10

    申请号：US11651614

    申请日：2007-01-08

    申请人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    发明人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    IPC分类号： H01L23/52

    CPC分类号： H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.

    摘要翻译： 集成电路芯片的I / O区域内的第一电路与芯片的芯区域内的第二电路之间的连接。 第一电路通过I / O区域的第一层中的第一导体连接到焊盘。 第二电路通过位于第一层上方的I / O区域的第二层中的第二导体连接到焊盘。

    Connection between an I/O region and the core region of an integrated circuit
    8.
    发明授权
    Connection between an I/O region and the core region of an integrated circuit 有权
    I / O区域与集成电路的核心区域之间的连接

    公开(公告)号：US08304813B2

    公开(公告)日：2012-11-06

    申请号：US11651614

    申请日：2007-01-08

    申请人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    发明人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    IPC分类号： H01L27/118

    CPC分类号： H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.

    摘要翻译： 集成电路芯片的I / O区域内的第一电路与芯片的芯区域内的第二电路之间的连接。 第一电路通过I / O区域的第一层中的第一导体连接到焊盘。 第二电路通过位于第一层上方的I / O区域的第二层中的第二导体连接到焊盘。