利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.029 秒)

    Guard region and hither plane vertex modification for graphics rendering
    1.
    发明授权
    Guard region and hither plane vertex modification for graphics rendering 失效
    保护区域和图形渲染的平面顶点修改

    公开(公告)号：US6144387A

    公开(公告)日：2000-11-07

    申请号：US55094

    申请日：1998-04-03

    申请人： Mei-Chi Liu ,  Adrian Sfarti ,  Adam Malamy ,  Nicholas Baker ,  John Cumming

    发明人： Mei-Chi Liu ,  Adrian Sfarti ,  Adam Malamy ,  Nicholas Baker ,  John Cumming

    IPC分类号： G06T15/30 ,  G06T15/10

    CPC分类号： G06T15/30

    摘要： Performing graphics rendering without the computational expense of hither plane clipping and with only a minimum of display image clipping. Where a three dimensional polygon crosses to both sides of a hither plane, any vertices on the back side of the hither plane are translated to the hither plane, producing polygons which occupy only the area in front of the hither plane. A display image memory, from which display images are generated, is located within a larger guard memory such that many images which would need to be clipped to fit in the display image memory may be written to the guard memory without clipping.

    摘要翻译： 执行图形渲染，而不需要平面裁剪的计算费用，只有最小的显示图像裁剪。 在三维多边形与两个平面的两侧相交的位置上，任一平面的背面上的任何顶点都被平移到两个平面，产生仅在该平面前面区域的多边形。 生成显示图像的显示图像存储器位于更大的保护存储器内，使得需要被剪切以适合显示图像存储器的许多图像可以被写入保护存储器而不会被削波。

    Applying multiple texture maps to objects in three-dimensional imaging processes
    3.
    发明申请
    Applying multiple texture maps to objects in three-dimensional imaging processes 有权

    公开(公告)号：US20050285873A1

    公开(公告)日：2005-12-29

    申请号：US11216251

    申请日：2005-08-31

    申请人： Nicholas Baker ,  Jeffrey Andrews ,  Mei-Chi Liu

    发明人： Nicholas Baker ,  Jeffrey Andrews ,  Mei-Chi Liu

    IPC分类号： G06T15/20 ,  G09G5/00

    CPC分类号： G06T15/04

    摘要： Systems and methods for providing multi-pass rendering of three-dimensional objects. A rendering pipeline that includes (N) physical texture units and one or more associated buffers emulates a rendering pipeline containing more texture units (M) than are physically present (N). Multiple rendering passes are performed for each pixel. During each texture pass only N sets of texture coordinates are passed to the texture units. The number of passes required through the pipeline to emulate M texture units is M/N, rounded up to the next integer. The N texture units of the rendering pipeline perform look-ups on a given pass for the corresponding N texture maps. The texture values obtained during the texture passes are blended by texture blenders to provide composite texture values. In successive passes, the buffers are used for temporary data and the most current composite texture values. The process is repeated until all desired texture maps are applied.

    Cheque processor
    5.
    发明授权
    Cheque processor 失效
    检查处理器

    公开(公告)号：US06837424B2

    公开(公告)日：2005-01-04

    申请号：US10208902

    申请日：2002-07-31

    申请人： Alex Young ,  Leonie Catherine Roberts ,  Terrence Alexander O'Donnell ,  Christopher John Perfect ,  Nicholas Baker ,  Iain MacPhail

    发明人： Alex Young ,  Leonie Catherine Roberts ,  Terrence Alexander O'Donnell ,  Christopher John Perfect ,  Nicholas Baker ,  Iain MacPhail

    IPC分类号： G07D11/00 ,  G07F19/00 ,  G06F17/00

    CPC分类号： G07F19/20 ,  G06Q20/042 ,  G07D11/0018

    摘要： The present invention provides an apparatus for processing of checks and includes a closed casing (1) having an opening defining a feed path (5) for the insertion of a check, and an optical scanner (3) for receiving a check fed into the casing (1) and recording data representing information on the face of the check. The apparatus includes a cancellation device (4) to cancel the check concurrently with the scanning and a communications device (2,9) for transmitting recorded data to a remote location. The invention is intended for distribution to end users, the drawees of checks, or as a component part of an automatic teller machine, such that a bank can trust that a digital check received from the apparatus via a communications network is as secure against being fraudulently deposited as if the check had been physically delivered in the conventional manner.

    摘要翻译： 本发明提供了一种用于检查的处理装置，并且包括具有限定用于插入支票的进给路径（5）的开口的封闭壳体（1），以及用于接收馈送到壳体中的支票的光学扫描器（3） （1），记录表示检查面的信息的数据。 该装置包括用于与扫描同时取消检查的取消装置（4）和用于将记录的数据发送到远程位置的通信装置（2,9）。 本发明旨在分发给最终用户，检查人员或作为自动取款机的组成部分，使得银行可以信任经由通信网络从设备接收到的数字检查作为欺骗性的安全性 存放好像是以常规方式物理交付支票一样。

    System and method for parallel execution of data generation tasks
    6.
    发明申请
    System and method for parallel execution of data generation tasks 审中-公开
    并行执行数据生成任务的系统和方法

    公开(公告)号：US20060095672A1

    公开(公告)日：2006-05-04

    申请号：US11065343

    申请日：2005-02-25

    申请人： Jeffrey Andrews ,  Nicholas Baker ,  J. Goossen ,  Michael Abrash ,  Russell Hoover ,  Eric Mejdrich ,  Sandra Woodward

    发明人： Jeffrey Andrews ,  Nicholas Baker ,  J. Goossen ,  Michael Abrash ,  Russell Hoover ,  Eric Mejdrich ,  Sandra Woodward

    IPC分类号： G06F12/14

    CPC分类号： G06F15/7846

    摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data

    摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。 每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。 输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。 在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在 高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期性地将尾部指针转发到数据生成元素内的可缓存位置，以向数据生成元素通知其在检索输出数据中的进度

    System and method for parallel execution of data generation tasks
    8.
    发明申请
    System and method for parallel execution of data generation tasks 失效

    公开(公告)号：US20050122339A1

    公开(公告)日：2005-06-09

    申请号：US11027454

    申请日：2004-12-30

    申请人： Jeffrey Andrews ,  Nicholas Baker ,  J. Goossen ,  Michael Abrash

    发明人： Jeffrey Andrews ,  Nicholas Baker ,  J. Goossen ,  Michael Abrash

    IPC分类号： G06F12/08 ,  G06F9/46 ,  G06F9/50 ,  G06F13/28 ,  G06F15/16 ,  G06F15/78 ,  G06F15/80 ,  G06T1/60 ,  G06T15/00 ,  G09G5/36

    CPC分类号： G06F15/7846

    摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.