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公开(公告)号：US4219283A
公开(公告)日：1980-08-26
申请号：US897039
申请日：1978-04-17
摘要： A removable closure for a hollow container carries a member for dispensing the contents of the container and the member is mounted on the closure for movement between a retracted position within the container when the closure is secured on the container and an extended position in which the member may contact substantially all parts of the interior of the container when the closure is removed from the container.
摘要翻译： 用于中空容器的可拆卸的封闭件承载用于分配容器的内容物的构件，并且当封闭件固定在容器上时，构件安装在封闭件上用于在容器内的缩回位置之间移动，并且其中构件 当封闭物从容器中取出时，可以基本接触容器内部的所有部分。
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公开(公告)号：US5787494A
公开(公告)日：1998-07-28
申请号：US532948
申请日：1995-09-22
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more complex and less common TLB misses and provides flexibility in the virtual memory management system.
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3.发明授权Method for decreasing time penalty resulting from a cache miss in a multi-level cache system 失效用于减少由多级缓存系统中的高速缓存未命中引起的时间损失的方法
公开(公告)号：US5603004A
公开(公告)日：1997-02-11
申请号：US196042
申请日：1994-02-14
CPC分类号： G06F12/0897 , G06F12/0864 , G06F12/12 , G06F12/0862
摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.
摘要翻译： 缓存系统缓冲存储在主存储器中并由处理器使用的数据。 高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。 第一个缓存是完全关联的。 第二个缓存直接映射。 第一个传输通道将数据线从主存储器传输到第一个缓存。 第二传输信道将数据线从第一高速缓存传送到第二高速缓存。 第三传送通道将数据线从第二高速缓存传送到主存储器。 并行执行来自第一高速缓存和第二高速缓存的数据线的访问。
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公开(公告)号：US5493660A
公开(公告)日：1996-02-20
申请号：US957345
申请日：1992-10-06
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more complex and less common TLB misses and provides flexibility in the virtual memory management system.
摘要翻译： 本发明提供了一种软件辅助硬件TLB未命中处理器，其被设计为在实现低成本并且需要很少的芯片面积或复杂性的情况下降低TLB错误代价。 当发生TLB未命中时，本发明的HW TLB未命中处理器基于丢失的虚拟地址来计算位于特殊硬件可见表中的页表项的物理地址。 它访问页表条目并检查正确的翻译和状态信息。 如果正确，页面表项的物理页面地址和保护信息被插入到TLB中。 原始虚拟地址被重新翻译，并且继续正常的程序执行。 如果找不到正确的翻译和状态，则HW TLB未命中处理程序将不会插入该条目，并将陷阱到更复杂的SW TLB未命中处理程序。 指向页表条目的指针被传递给SW TLB未命中处理程序，以便不需要重新计算页表地址。 因此，本发明的HW TLB未命中处理器非常快速地服务于最简单和最常见的TLB未命中，从而降低了总体TLB的丢失率。 较慢的SW TLB错误处理程序服务于更复杂和更不常见的TLB未命中，并在虚拟内存管理系统中提供灵活性。
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