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    Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
    1.
    发明授权
    Method for decreasing time penalty resulting from a cache miss in a multi-level cache system 失效
    用于减少由多级缓存系统中的高速缓存未命中引起的时间损失的方法

    公开(公告)号：US5603004A

    公开(公告)日：1997-02-11

    申请号：US196042

    申请日：1994-02-14

    申请人： Gordon Kurpanek ,  Eric Delano ,  Michael A. Buckley ,  William R. Bryg

    发明人： Gordon Kurpanek ,  Eric Delano ,  Michael A. Buckley ,  William R. Bryg

    IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/0862

    摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.

    摘要翻译： 缓存系统缓冲存储在主存储器中并由处理器使用的数据。 高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。 第一个缓存是完全关联的。 第二个缓存直接映射。 第一个传输通道将数据线从主存储器传输到第一个缓存。 第二传输信道将数据线从第一高速缓存传送到第二高速缓存。 第三传送通道将数据线从第二高速缓存传送到主存储器。 并行执行来自第一高速缓存和第二高速缓存的数据线的访问。

    Method and apparatus for checking cache coherency in a computer architecture
    2.
    发明授权
    Method and apparatus for checking cache coherency in a computer architecture 失效
    用于在计算机体系结构中检查高速缓存一致性的方法和装置

    公开(公告)号：US06049851A

    公开(公告)日：2000-04-11

    申请号：US196618

    申请日：1994-02-14

    申请人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

    发明人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

    IPC分类号： G06F12/08 ,  G06F9/34

    CPC分类号： G06F12/0831

    摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

    摘要翻译： 具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。 侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在 需要修改缓存。 即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。

    System and method for memory migration in distributed-memory multi-processor systems
    3.
    发明授权
    System and method for memory migration in distributed-memory multi-processor systems 失效
    分布式存储器多处理器系统中内存迁移的系统和方法

    公开(公告)号：US07103728B2

    公开(公告)日：2006-09-05

    申请号：US10201180

    申请日：2002-07-23

    申请人： Debendra Das Sharma ,  Ashish Gupta ,  William R. Bryg

    发明人： Debendra Das Sharma ,  Ashish Gupta ,  William R. Bryg

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0813 ,  G06F12/0817

    摘要： A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.

    摘要翻译： 分布式存储器多处理器系统包括通信地彼此耦合并且共同包括多个处理器，高速缓存，主存储器和单元控制器的多个单元。 每个单元包括至少一个处理器，高速缓存，主存储器中的一个和单元控制器之一中的至少一个。 每个单元被配置为执行存储器迁移功能，用于以对系统的操作系统不可见的方式将存储器从主存储器中的第一存储器迁移到主存储器中的第二存储器。

    System and method for memory interleaving using cell map with entry grouping for higher-way interleaving
    4.
    发明授权
    System and method for memory interleaving using cell map with entry grouping for higher-way interleaving 有权
    使用具有入口分组的小区映射进行存储器交错的系统和方法用于较高路交织

    公开(公告)号：US06874070B2

    公开(公告)日：2005-03-29

    申请号：US10080440

    申请日：2002-02-22

    申请人： Ashish Gupta ,  William R. Bryg

    发明人： Ashish Gupta ,  William R. Bryg

    IPC分类号： G06F15/167 ,  G06F12/06 ,  G06F15/177 ,  G06F12/00

    CPC分类号： G06F12/0607

    摘要： A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.

    摘要翻译： 使用连续逻辑地址空间以交错方式访问多个存储器的方法包括提供至少一个映射表。 所述至少一个地图表包括多个条目。 每个条目包括多个条目项。 每个条目项标识其中一个存储器。 接收到第一个逻辑地址。 第一逻辑地址包括多个地址位。 多个地址位包括与至少一个映射表中的第一组条目相对应的第一组地址位。 基于第一组和第二组地址位来识别第一组条目中的第一条目。 基于第三组地址位来识别第一条目中的第一条目项目。 由第一个条目项目识别的存储器被访问。

    Apparatus and method for a load bias--load with intent to semaphore
    6.
    发明授权
    Apparatus and method for a load bias--load with intent to semaphore 失效
    用于信号量的负载偏置负载的装置和方法

    公开(公告)号：US6128706A

    公开(公告)日：2000-10-03

    申请号：US018165

    申请日：1998-02-03

    申请人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    发明人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    IPC分类号： G06F9/312 ,  G06F13/00

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087

    摘要： Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.

    摘要翻译： 用于有效地共享数据以支持硬件高速缓存一致性并利用信号量指令在软件中协调的装置和方法。 因此，称为“负载偏置”的新指令除了正常的加载操作之外，还请求数据的私有副本，并向硬件缓存提示，以尝试维持所有权，直到来自该处理器的下一个存储器引用。 当与Cmpxchg指令信号量操作一起使用时，负载偏移指令将减少一致性流量，并最大限度地减少一致性乒乓或系统死锁的可能性，从而导致无处理器无法正常工作的条件。

    Method and apparatus for instruction and data serialization in a computer processor
    7.
    发明授权
    Method and apparatus for instruction and data serialization in a computer processor 失效
    计算机处理器中指令和数据串行化的方法和装置

    公开(公告)号：US6006325A

    公开(公告)日：1999-12-21

    申请号：US769784

    申请日：1996-12-19

    申请人： Stephen Burger ,  Gary N. Hammond ,  William R. Bryg

    发明人： Stephen Burger ,  Gary N. Hammond ,  William R. Bryg

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/30087 ,  G06F9/3834

    摘要： A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.

    摘要翻译： 介绍了一个新的指令，确保控制寄存器写入的效果将在明确的时间内被观察到。 具体地，本发明引入了序列化栅栏指令的概念。 序列化栅栏指令确保在计算机中的控制寄存器已被修改后，所有后续指令将观察到控制寄存器修改的影响。 说明了两个不同的序列化栅栏指令：数据存储器引用序列化栅栏指令（SRLZ.d）和指令获取序列化栅栏指令（SRLZ.i）。 数据存储器引用序列化栅栏指令确保后续指令执行和数据存储器引用将观察到控制寄存器写入的影响。 指令获取序列化栅栏指令确保从初始指令读取阶段开始的整个机器流水线将观察到控制寄存器写入的影响。

    Fast pipelined distributed arbitration scheme
    8.
    发明授权
    Fast pipelined distributed arbitration scheme 失效
    快速流水线分布仲裁方案

    公开(公告)号：US5519838A

    公开(公告)日：1996-05-21

    申请号：US201186

    申请日：1994-02-24

    申请人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

    发明人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

    IPC分类号： G06F13/368 ,  G06F13/00

    CPC分类号： G06F13/368

    摘要： A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

    摘要翻译： 具有总线仲裁方案的总线系统。 总线系统包括总线和耦合到总线的多个客户端模块。 每个客户端模块能够将总线上的信息发送到客户端模块的另一个，只有一个客户端模块有权在任何时候在总线上传输信息。 有权在总线上传输信息的模块可以控制总线最短时间来定义一个周期。 为了确定哪个模块有权使用总线，当客户端模块试图在总线上传输信息时，每个客户端模块都会产生仲裁信号。 每个客户端模块具有响应于仲裁信号的仲裁信号处理器，用于确定模块是否有权在所述总线上发送信息。 系统还优选地还包括主机模块，其向客户端模块通知在给定周期中在总线上允许的交易类型。 每个仲裁信号处理器优选地还响应于在较早的周期期间由主机模块发送的客户端选项信号。