Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design
    1.
    发明授权
    Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design 失效
    用于提取和存储深亚微米集成电路设计的连接性和几何数据的方法和装置

    公开(公告)号:US06230299B1

    公开(公告)日:2001-05-08

    申请号:US09052895

    申请日:1998-03-31

    IPC分类号: G06S1750

    CPC分类号: G06F17/5081

    摘要: A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.

    摘要翻译: 提供数据提取工具来提取用于集成电路(IC)设计的指定布局单元层级的滤波连接性和几何数据。 深亚微米IC设计。 至少部分地根据指定的寄生效应窗口提取每个布局单元层级的连接性和几何数据。 在一个实施例中,数据提取工具包括滤波提取功能,其操作以提取用于IC设计的每个布局单元层次结构的布局网络的连接性和几何数据,一次一个或多个布局网。 另外,提供了一个或多个过滤的数据库以存储布局单元层次结构的经滤波的连接和几何数据。

    Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design
    2.
    发明授权
    Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design 失效
    用于生成和维护深亚微米集成电路设计的电气建模数据的方法和装置

    公开(公告)号:US06249903B1

    公开(公告)日:2001-06-19

    申请号:US09052915

    申请日:1998-03-31

    IPC分类号: G06F1750

    CPC分类号: G06F17/5081

    摘要: A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e.g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.

    摘要翻译: 提供寄生提取工具(PEX)以产生集成电路(IC)设计的电气建模数据,例如。 深亚微米IC设计。 PEX包括用于读取提取的连接性和IC设计的各种布局单元层级的几何数据的读取功能,其由布局网组织和索引。 PEX还包括写入功能,用于将生成的电气建模数据写入到寄生数据库(PDB)中,寄生数据库(PDB)被物理组织以适应多个物理介质中的电气建模数据的物理存储,以及多个客户端应用程序的电气数据的并发使用 ,例如 后期布局分析工具。 在一个实施例中,PDB还包括屏蔽PDB的物理组织的应用接口以及物理组织的逻辑抽象以促进应用接口的实现。

    Method and mechanism for implementing extraction for an integrated circuit design
    3.
    发明授权
    Method and mechanism for implementing extraction for an integrated circuit design 有权
    实现集成电路设计提取的方法和机制

    公开(公告)号:US08375342B1

    公开(公告)日:2013-02-12

    申请号:US12987064

    申请日:2011-01-07

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

    摘要翻译: 公开了一种用于在集成电路设计上执行提取的改进的方法和系统。 可以以比整个IC设计小得多的粒度执行提取,其中使用光晕来识别围绕感兴趣对象的几何体积以识别相邻对象并生成电模型。 提取方法可以用于群岛,网络以及设计中的其他粒度。 设计的重新提取可能发生在小于网格的粒度上。 一些方法利用岛缝来替代网内的岛屿。 还描述了一种改进交叉耦合对象的交叉引用的方法。

    Method and mechanism for implementing extraction for an integrated circuit design
    4.
    发明授权
    Method and mechanism for implementing extraction for an integrated circuit design 有权
    实现集成电路设计提取的方法和机制

    公开(公告)号:US08635574B1

    公开(公告)日:2014-01-21

    申请号:US12987067

    申请日:2011-01-07

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

    摘要翻译: 公开了一种用于在集成电路设计上执行提取的改进的方法和系统。 可以以比整个IC设计小得多的粒度执行提取,其中使用光晕来识别围绕感兴趣对象的几何体积以识别相邻对象并生成电模型。 提取方法可以用于群岛,网络以及设计中的其他粒度。 设计的重新提取可能发生在小于网格的粒度上。 一些方法利用岛缝来替代网内的岛屿。 还描述了一种改进交叉耦合对象的交叉引用的方法。

    Method and mechanism for implementing extraction for an integrated circuit design
    5.
    发明授权
    Method and mechanism for implementing extraction for an integrated circuit design 有权
    实现集成电路设计提取的方法和机制

    公开(公告)号:US08316331B1

    公开(公告)日:2012-11-20

    申请号:US12987072

    申请日:2011-01-07

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched.

    摘要翻译: 公开了一种用于拼接集成电路设计的一个或多个岛的改进的方法和系统。 首先确定IC设计中的多个连接岛对象。 然后修改多个确定的连接的岛对象中的至少一个以形成修改的岛对象。 然后可以将经修改的岛屿物体缝合到多个识别的连接的岛屿物体中。 在一些实施例中,缝合修改的岛屿对象可以通过跟踪被修改和缝合的连接的岛对象的端点,端口或节点来实现。

    Method and mechanism for implementing extraction for an integrated circuit design
    6.
    发明授权
    Method and mechanism for implementing extraction for an integrated circuit design 有权
    实现集成电路设计提取的方法和机制

    公开(公告)号:US07870517B1

    公开(公告)日:2011-01-11

    申请号:US11741699

    申请日:2007-04-27

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction can be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

    摘要翻译: 公开了一种用于在集成电路设计上执行提取的改进的方法和系统。 可以以比整个IC设计小得多的粒度执行提取,其中使用光晕来识别围绕感兴趣对象的几何体,以识别相邻对象并生成电模型。 提取方法可以用于群岛,网络以及设计中的其他粒度。 设计的重新提取可能发生在小于网格的粒度上。 一些方法利用岛缝来替代网内的岛屿。 还描述了一种改进交叉耦合对象的交叉引用的方法。