-
公开(公告)号：US07206916B2
公开(公告)日：2007-04-17
申请号：US10795815
申请日：2004-03-08
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, and using the result of the more significant bit compare in conjunction with results from a compare of less significant bits of the information and less significant bits of compare information to determine whether a match is present. The more significant bit compare compares more significant bits of the information being loaded into the translation lookaside buffer with more significant bits of compare information.
摘要翻译： 一种在处理器内执行快速信息比较的方法，包括当信息被加载到翻译后备缓冲器中时执行更重要的位比较，将翻译后备缓冲器内的更高有效位比较的结果存储在包含 并且将结果与比较信息的较低有效位的比较结果和比较信息的较低有效比特结果进行比较，以确定是否存在匹配。 更重要的比较比较将加载到翻译后备缓冲器中的信息的更高有效位与更多比较的比较信息比较。
-
公开(公告)号：US06794902B2
公开(公告)日：2004-09-21
申请号：US10172574
申请日：2002-06-14
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01728
摘要： Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.
摘要翻译： 描述了用于改进逻辑电路的方法和系统。 通过使用用于将电源连接到虚拟接地的电压减小器，降压器在时钟的一个相位期间将由电源供给的电压降低到虚拟接地，从而提高逻辑电路的速度和效率。
-
搜索结果
2 条记录 (耗时 0.018 秒)
