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    PROCESSOR WITH INCREASED EFFICIENCY VIA CONTROL WORD PREDICTION
    1.
    发明申请
    PROCESSOR WITH INCREASED EFFICIENCY VIA CONTROL WORD PREDICTION 有权
    处理器通过控制字预测提高效率

    公开(公告)号：US20120226891A1

    公开(公告)日：2012-09-06

    申请号：US13037830

    申请日：2011-03-01

    申请人： Michael D. ESTLICK ,  Jay FLEISCHMAN ,  Debjit Das Sarma ,  Emil TALPES ,  Krishnan V. RAMANI ,  Chun LIU

    发明人： Michael D. ESTLICK ,  Jay FLEISCHMAN ,  Debjit Das Sarma ,  Emil TALPES ,  Krishnan V. RAMANI ,  Chun LIU

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3861 ,  G06F9/30094 ,  G06F9/3842

    摘要： Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.

    摘要翻译： 提供了通过控制字预测提高处理器效率的方法和装置。 该装置包括一个操作单元，其能够确定指令是否将第一控制字改变为第二控制字以用于处理相关指令。 执行单元使用预测的控制字处理依赖指令，并将第二控制字与预测的控制字进行比较。 当预测控制字与第二控制字不匹配时，调度单元使执行单元重新处理依赖指令。 该方法包括确定指令将第一控制字改变为第二控制字，并使用预测的控制字处理依赖指令。 将第二控制字与预测的控制字进行比较，并且当预测控制字与第二控制字不匹配时，使用第二控制字重新处理依赖指令。

    Processor with increased efficiency via early instruction completion
    3.
    发明授权
    Processor with increased efficiency via early instruction completion 有权
    处理器通过早期指令完成提高效率

    公开(公告)号：US08769247B2

    公开(公告)日：2014-07-01

    申请号：US13088096

    申请日：2011-04-15

    申请人： Michael D Estlick ,  Kevin Hurd ,  Jay Fleischman

    发明人： Michael D Estlick ,  Kevin Hurd ,  Jay Fleischman

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3855

    摘要： Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.

    摘要翻译： 提供了通过早期指令完成来提高处理器的效率的方法和装置。 提供了一种通过早期指令完成来提高处理器的效率的装置。 该装置包括执行单元，用于处理指令并确定稍后发出的指令是否准备好完成，或者较早发出的指令准备好完成;以及退出单元，用于在稍后的指令准备完成或退出时退出稍后发出的指令 后期指令未准备好完成的早期指令，并且较早发出的指令具有已知的良好完成状态。 提供了一种通过早期指令完成来提高处理器的效率的方法。 该方法包括当稍后发出的指令未准备好完成时，完成先前发出的指令，该指令在稍后发出的指令之前具有已知的良好完成状态。

    Processor with increased efficiency via control word prediction
    4.
    发明授权
    Processor with increased efficiency via control word prediction 有权
    处理器通过控制字预测提高效率

    公开(公告)号：US08819397B2

    公开(公告)日：2014-08-26

    申请号：US13037830

    申请日：2011-03-01

    申请人： Michael D. Estlick ,  Jay Fleischman ,  Debjit Das Sarma ,  Emil Talpes ,  Krishnan V. Ramani ,  Chun Liu

    发明人： Michael D. Estlick ,  Jay Fleischman ,  Debjit Das Sarma ,  Emil Talpes ,  Krishnan V. Ramani ,  Chun Liu

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3861 ,  G06F9/30094 ,  G06F9/3842

    摘要： Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.

    摘要翻译： 提供了通过控制字预测提高处理器效率的方法和装置。 该装置包括一个操作单元，其能够确定指令是否将第一控制字改变为第二控制字以用于处理相关指令。 执行单元使用预测的控制字处理依赖指令，并将第二控制字与预测的控制字进行比较。 当预测控制字与第二控制字不匹配时，调度单元使执行单元重新处理依赖指令。 该方法包括确定指令将第一控制字改变为第二控制字，并使用预测的控制字处理依赖指令。 将第二控制字与预测的控制字进行比较，并且当预测控制字与第二控制字不匹配时，使用第二控制字重新处理依赖指令。

    PROCESSOR WITH INCREASED EFFICIENCY VIA EARLY INSTRUCTION COMPLETION
    5.
    发明申请
    PROCESSOR WITH INCREASED EFFICIENCY VIA EARLY INSTRUCTION COMPLETION 有权
    处理器通过早期指导性完成提高效率

    公开(公告)号：US20120265966A1

    公开(公告)日：2012-10-18

    申请号：US13088096

    申请日：2011-04-15

    申请人： Michael D. ESTLICK ,  Kevin HURD ,  Jay FLEISCHMAN

    发明人： Michael D. ESTLICK ,  Kevin HURD ,  Jay FLEISCHMAN

    IPC分类号： G06F9/32 ,  G06F9/44

    CPC分类号： G06F9/3855

    摘要： Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.

    摘要翻译： 提供了通过早期指令完成来提高处理器效率的方法和装置。 提供了一种通过早期指令完成来提高处理器的效率的装置。 该装置包括执行单元，用于处理指令并确定稍后发出的指令是否准备好完成，或者较早发出的指令准备好完成;以及退出单元，用于在稍后的指令准备完成或退出时退出稍后发出的指令 后期指令未准备好完成的早期指令，并且较早发出的指令具有已知的良好完成状态。 提供了一种通过早期指令完成来提高处理器的效率的方法。 该方法包括当稍后发出的指令未准备好完成时，完成先前发出的指令，该指令在稍后发出的指令之前具有已知的良好完成状态。

    Partial address compares stored in translation lookaside buffer
    6.
    发明授权
    Partial address compares stored in translation lookaside buffer 有权
    部分地址比较存储在翻译后备缓冲区中

    公开(公告)号：US07206916B2

    公开(公告)日：2007-04-17

    申请号：US10795815

    申请日：2004-03-08

    申请人： Michael D. Estlick ,  Harry R. Fair, III ,  David R. Akeson

    发明人： Michael D. Estlick ,  Harry R. Fair, III ,  David R. Akeson

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F11/3471 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    摘要： A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, and using the result of the more significant bit compare in conjunction with results from a compare of less significant bits of the information and less significant bits of compare information to determine whether a match is present. The more significant bit compare compares more significant bits of the information being loaded into the translation lookaside buffer with more significant bits of compare information.

    摘要翻译： 一种在处理器内执行快速信息比较的方法，包括当信息被加载到翻译后备缓冲器中时执行更重要的位比较，将翻译后备缓冲器内的更高有效位比较的结果存储在包含 并且将结果与比较信息的较低有效位的比较结果和比较信息的较低有效比特结果进行比较，以确定是否存在匹配。 更重要的比较比较将加载到翻译后备缓冲器中的信息的更高有效位与更多比较的比较信息比较。