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12 条记录 (耗时 0.028 秒)

    Physical resynthesis of a logic design
    1.
    发明授权
    Physical resynthesis of a logic design 失效
    逻辑设计的物理再合成

    公开(公告)号：US07337100B1

    公开(公告)日：2008-02-26

    申请号：US10461921

    申请日：2003-06-12

    申请人： Michael D. Hutton ,  Joachim Pistorius ,  Babette van Antwerpen ,  Gregg Baeckler ,  Richard Yuan ,  Yean-Yow Hwang

    发明人： Michael D. Hutton ,  Joachim Pistorius ,  Babette van Antwerpen ,  Gregg Baeckler ,  Richard Yuan ,  Yean-Yow Hwang

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G01R31/28

    CPC分类号： G06F17/5068

    摘要： A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

    摘要翻译： 多通道合成技术提高了设计的性能。 在具体实施方案中，以两次或更多次通过进行合成。 在第一次通过中，执行第一次合成，并且在第二次或随后的过程中进行第二次合成或再合成。 在第一合成期间，逻辑将被映射到例如目标技术的逻辑结构（例如，逻辑元件，LUT，合成门），诸如可编程逻辑器件。 或者，可以从第三方提供网表。 在第二合成之前，可以将网表快速或缩写配合到特定设备（例如，特定的可编程逻辑设备产品）。 在第二次合成之前，从第一次合成（或由第三方提供）获得的网表被未映射，然后进行第二次合成。 由于执行部分拟合，所以第二合成比通过使用单个合成通路更好的可见性和优化逻辑。 在第二次合成之后，进行更详细的拟合。

    Register retiming technique
    2.
    发明授权
    Register retiming technique 有权

    公开(公告)号：US07120883B1

    公开(公告)日：2006-10-10

    申请号：US10446650

    申请日：2003-05-27

    申请人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    发明人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

    Register retiming technique
    3.
    发明授权
    Register retiming technique 有权
    注册重新定时技术

    公开(公告)号：US08108812B1

    公开(公告)日：2012-01-31

    申请号：US12749514

    申请日：2010-03-30

    申请人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    发明人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

    摘要翻译： 电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。 寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。 在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。 系统平衡时间，以便折中关键路径和非关键路径之间的延迟。 注册重新定时可能会改变门级设计。

    Register retiming technique
    4.
    发明授权
    Register retiming technique 失效
    注册重新定时技术

    公开(公告)号：US07689955B1

    公开(公告)日：2010-03-30

    申请号：US11513450

    申请日：2006-08-30

    申请人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    发明人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

    摘要翻译： 电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。 寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。 在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。 系统平衡时间，以便折中关键路径和非关键路径之间的延迟。 注册重新定时可能会改变门级设计。

    Register retiming technique
    5.
    发明授权
    Register retiming technique 有权

    公开(公告)号：US08402408B1

    公开(公告)日：2013-03-19

    申请号：US13338776

    申请日：2011-12-28

    申请人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    发明人： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

    Estimating quality during early synthesis
    6.
    发明授权
    Estimating quality during early synthesis 有权
    早期综合评估质量

    公开(公告)号：US07171633B1

    公开(公告)日：2007-01-30

    申请号：US10734905

    申请日：2003-12-12

    申请人： Yean-Yow Hwang ,  Babette van Antwerpen ,  Richard Yuan

    发明人： Yean-Yow Hwang ,  Babette van Antwerpen ,  Richard Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmable logic integrated circuit. In a specific implementation, the invention incorporates late-stage synthesis operations, such as found during a technology mapping operation, into earlier stage synthesis procedures. These late-stage synthesis operations are used to provide better estimates of delay and area of a final compiled design in order to guide optimization operations.

    摘要翻译： 计算机辅助系统包括提高逻辑功能的合成和映射到诸如可编程逻辑的逻辑单元（例如，查找表）的目标技术的逻辑结构中的精度，优化和最小化的方法 集成电路。 在具体实现中，本发明将晚期合成操作（诸如在技术映射操作期间发现）融入到早期阶段合成过程中。 这些后期综合操作用于提供对最终编译设计的延迟和面积的更好估计，以指导优化操作。

    Fast method for functional mapping to incomplete LUT pairs
    9.
    发明申请
    Fast method for functional mapping to incomplete LUT pairs 有权
    用于功能映射到不完整LUT对的快速方法

    公开(公告)号：US20070035327A1

    公开(公告)日：2007-02-15

    申请号：US11201565

    申请日：2005-08-10

    申请人： Gregg Baeckler ,  Babette van Antwerpen

    发明人： Gregg Baeckler ,  Babette van Antwerpen

    IPC分类号： H03K19/173

    CPC分类号： G06F17/5054

    摘要： A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.

    摘要翻译： 确定可编程设备的配置以使用至少两个逻辑单元实现不完整的功能。 功能输入被分成与第一和第二逻辑单元相关联的部分。 筛选分区以通过确定是否可以使用完整的查找表来实现功能的一部分来确定它是否可以接受。 如果函数输入的分区是潜在可接受的，则将功能输入分配给逻辑单元的输入端口。 变量被分配给查找表位置，并且在功能输入和输出值，变量和查找表位置之间确定对应关系。 将布尔重言规则应用于对应关系，以简化变量。 如果简化的变量是一致的，则输出配置，其中包括基于简化变量对输入端口的功能输入和查找表数据的分配。

    State machine recognition and optimization
    10.
    发明授权
    State machine recognition and optimization 有权
    状态机识别和优化

    公开(公告)号：US07441212B1

    公开(公告)日：2008-10-21

    申请号：US11222090

    申请日：2005-09-07

    申请人： Babette van Antwerpen ,  Gregg William Baeckler

    发明人： Babette van Antwerpen ,  Gregg William Baeckler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each strongly connected component are identified. An optimal set of inputs and potential state transition logic is identified for the registers in the component. A set of reachable states from an initial state of the registers of a component is determined by simulating state transitions in response to permutations of input values. State machine information is created to assist compilation software in optimizing the user design. Optimizations can include identifying redundant circuit elements based on the set of reachable states and reencoding the state machine with a different state encoding scheme to reduce the amount of state transition and output logic. A subset of the set of reachable states representing a one-hot encoded state machine may be further isolated and optimized.

    摘要翻译： 状态机由用户设计的电路元件的网表识别。 网表中的强大连接组件被确定为分析候选者。 识别每个强连接组件的寄存器。 为组件中的寄存器识别最佳的输入和潜在状态转换逻辑。 通过响应于输入值的排列来模拟状态转换来确定来自组件的寄存器的初始状态的一组可达状态。 创建状态机信息以帮助编译软件优化用户设计。 优化可以包括基于可达状态的集合识别冗余电路元件，并且用不同的状态编码方案重新编码状态机以减少状态转换和输出逻辑的量。 可以进一步隔离和优化代表单热编码状态机的一组可达状态的子集。