摘要:
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要:
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要:
Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要:
Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要:
Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要:
Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要:
Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要:
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要:
A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.
摘要:
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.