Register retiming technique
    8.
    发明授权

    公开(公告)号:US08402408B1

    公开(公告)日:2013-03-19

    申请号:US13338776

    申请日:2011-12-28

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5054 G06F17/5045

    摘要: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

    Physical resynthesis of a logic design
    9.
    发明授权
    Physical resynthesis of a logic design 失效
    逻辑设计的物理再合成

    公开(公告)号:US07337100B1

    公开(公告)日:2008-02-26

    申请号:US10461921

    申请日:2003-06-12

    IPC分类号: G06F17/50 G06F9/455 G01R31/28

    CPC分类号: G06F17/5068

    摘要: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

    摘要翻译: 多通道合成技术提高了设计的性能。 在具体实施方案中,以两次或更多次通过进行合成。 在第一次通过中,执行第一次合成,并且在第二次或随后的过程中进行第二次合成或再合成。 在第一合成期间,逻辑将被映射到例如目标技术的逻辑结构(例如,逻辑元件,LUT,合成门),诸如可编程逻辑器件。 或者,可以从第三方提供网表。 在第二合成之前,可以将网表快速或缩写配合到特定设备(例如,特定的可编程逻辑设备产品)。 在第二次合成之前,从第一次合成(或由第三方提供)获得的网表被未映射,然后进行第二次合成。 由于执行部分拟合,所以第二合成比通过使用单个合成通路更好的可见性和优化逻辑。 在第二次合成之后,进行更详细的拟合。

    Register retiming technique
    10.
    发明授权

    公开(公告)号:US07120883B1

    公开(公告)日:2006-10-10

    申请号:US10446650

    申请日:2003-05-27

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5054 G06F17/5045

    摘要: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.