公开(公告)号：US5635994A

公开(公告)日：1997-06-03

申请号：US351585

申请日：1994-12-07

申请人： Michael Drexler ,  Heinz-Werner Keesen ,  Carsten Herpel

发明人： Michael Drexler ,  Heinz-Werner Keesen ,  Carsten Herpel

IPC分类号： G06T9/00 ,  H04N19/523 ,  H04N19/53 ,  H04N7/32 ,  H04N7/50

CPC分类号： H04N19/53 ,  H04N19/523

摘要： A method of making a hierarchical estimate of image motion for a television signal. A television signal video image is divided into blocks of fixed size, and motion relative to a second video image is determined for each block. Mutually non-overlapping pixel blocks are produced at a lower, more finely resolved hierarchical level. The center points of these blocks are used as the points for an analysis at a level that is located higher in the hierarchy. Preferably, points which lie between image lines and which do not represent real picture elements in the line raster, are investigated in the mutually non-overlapping blocks.

摘要翻译： 对电视信号进行图像运动的分层估计的方法。 电视信号视频图像被分成固定大小的块，并且针对每个块确定相对于第二视频图像的运动。 相互不重叠的像素块以更低，更精细地分层的级别产生。 这些块的中心点用作层次结构中较高层次的分析点。 优选地，在相互不重叠的块中研究位于图像线之间并且不表示线条光栅中的实像元的点。

公开(公告)号：US08352780B2

公开(公告)日：2013-01-08

申请号：US12819432

申请日：2010-06-21

申请人： Thomas Brune ,  Michael Drexler ,  Dieter Haupt

发明人： Thomas Brune ,  Michael Drexler ,  Dieter Haupt

IPC分类号： G06F11/00

CPC分类号： G06F11/141 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C29/70

摘要： For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

摘要翻译： 对于写入，闪存设备以面向页面的模式进行物理访问，但是这样的设备在操作中不会出错。 根据本发明，当将总线写入周期中的信息数据以顺序的方式写入分配给公共数据总线的闪存器件中时，所述闪存器件中的至少一个不被馈送用于与所述信息数据的当前部分一起存储 。 如果在将当前信息数据部分写入当前所述闪速存储器件的页面中发生错误的情况下，将所述当前信息数据部分写入非闪存存储器。 在下一个总线写周期期间，当包含该故障页的闪存设备通常是空闲时，该空闲时间段用于将所述信息数据的相应存储部分从所述非闪存存储器复制到该非闪存存储器的非缺陷页 闪存设备。

公开(公告)号：US06414540B1

公开(公告)日：2002-07-02

申请号：US09737077

申请日：2000-12-14

申请人： Michael Drexler

发明人： Michael Drexler

IPC分类号： H04B110

摘要： An input filter stage and to a method for filtering a data stream. The input filter stage comprises a register chain, which is connected to an input line and has a plurality of series-connected registers, and a switching device connected to an output line and to the register chain in order to switch the output line, a signal input of a first register in the register chain being connected to the input line, and a signal input of a subsequent register in the register chain being connected to a respective signal output of a preceding register in the register chain, a clock input for the plurality of registers being connected to a respective clock line which can be used to transmit a sampling signal at a sampling frequency, the sampling frequency being higher than a maximum data transmission frequency of the data stream, and the switching device being connected to the register chain such that the output line can be switched to a logic level of the signal outputs of the plurality of registers when output signals which are produced at each of the signal outputs of the plurality of registers are at the same logic level.

公开(公告)号：US08548300B2

公开(公告)日：2013-10-01

申请号：US12291766

申请日：2008-11-13

申请人： Marco Winter ,  Michael Drexler

发明人： Marco Winter ,  Michael Drexler

IPC分类号： H04N5/76

CPC分类号： H04N5/907 ,  H04N5/765

摘要： The invention is related to a method and a device for recording of frames.Said method comprises buffering fractions of frames in a buffer and transferring from the buffer to memory devices data packets comprising at least one fraction, each, wherein after transferring to a first memory device a first fraction of a first frame, only fractions of said first frame are transferred to said first memory device until the amount of data belonging to said first frame and being transferred to said first memory device corresponds the storage capacity of at least one memory block comprised in said first memory device.

公开(公告)号：US20090142040A1

公开(公告)日：2009-06-04

申请号：US12291766

申请日：2008-11-13

申请人： Marco Winter ,  Michael Drexler

发明人： Marco Winter ,  Michael Drexler

IPC分类号： H04N5/91

CPC分类号： H04N5/907 ,  H04N5/765

摘要： The invention is related to a method and a device for recording of frames.Said method comprises buffering fractions of frames in a buffer and transferring from the buffer to memory devices data packets comprising at least one fraction, each, wherein after transferring to a first memory device a first fraction of a first frame, only fractions of said first frame are transferred to said first memory device until the amount of data belonging to said first frame and being transferred to said first memory device corresponds the storage capacity of at least one memory block comprised in said first memory device.

摘要翻译： 本发明涉及用于记录帧的方法和装置。 所述方法包括在缓冲器中缓冲一些帧，并将缓冲器从缓冲器传送到存储器装置，数据包包括至少一个分数，每个分组包括：在将第一帧的第一部分转移到第一存储器之后，仅将所述第一帧的分数 被转移到所述第一存储设备，直到属于所述第一帧并且被传送到所述第一存储设备的数据量对应于包括在所述第一存储器设备中的至少一个存储器块的存储容量。

公开(公告)号：US4818653A

公开(公告)日：1989-04-04

申请号：US922332

申请日：1986-10-23

申请人： Wolfgang Wiedemann ,  Michael Drexler ,  Juergen Fuerderer

发明人： Wolfgang Wiedemann ,  Michael Drexler ,  Juergen Fuerderer

IPC分类号： G03G5/00 ,  G03G5/04 ,  G03G5/06 ,  G03G5/07 ,  G03G5/14 ,  G03G5/09

CPC分类号： G03G5/0605 ,  G03G5/0637 ,  G03G5/0698 ,  G03G5/07 ,  Y10S430/10

摘要： An electrophotographic recording material is described that comprises an electrically conducting base layer and a photoconductive system deposited thereon, which system comprises an optional insulating intermediate layer, a layer containing a charge-generating compound, and a layer containing a charge-transporting compound mixed with binders, along with any sensitizers, acceptors and usual additives. The photoconductive system contains, as acceptor additive, one or more monomeric or polymeric compounds that have electron-attracting substitutents (halogen, cyano, nitro groups) and that are selected from the group consisting of anthracene, acridine, the anhydrides of phthalic acid, maleic acid, pyromellitic acid, benzophenonetetracarboxylic acid, and the polymers of vinyl chloride, vinylidine chloride and nitrocellulose, in a quantity of 0.2 to 10% by weight based on total coating weight. After erasure of the latent electrostatic image, the recording material has a low residual charge, even when operated cyclically. Background imaging is thereby avoided.

摘要翻译： 描述了一种电子照相记录材料，其包括沉积在其上的导电基底层和光导体系，该系统包括任选的绝缘中间层，含有产生电荷的化合物的层和含有与粘合剂混合的电荷输送化合物的层 ，以及任何敏化剂，受体和常用添加剂。 光导体系含有一个或多个具有吸电子取代基（卤素，氰基，硝基）的单体或聚合化合物作为受体添加剂，其选自蒽，吖啶，邻苯二甲酸酐，马来酸酐 酸，均苯四酸，二苯甲酮四羧酸，以及氯乙烯，氯乙烯和硝基纤维素的聚合物，以总涂料重量计为0.2〜10重量％。 在静电图像被擦除之后，即使循环操作，记录材料也具有低剩余电荷。 从而避免背景成像。

公开(公告)号：US20130138875A1

公开(公告)日：2013-05-30

申请号：US13816250

申请日：2011-08-08

申请人： Oliver Kamphenkel ,  Thomas Brune ,  Michael Drexler ,  Stefan Abeling

发明人： Oliver Kamphenkel ,  Thomas Brune ,  Michael Drexler ,  Stefan Abeling

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F13/1684 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7208

摘要： High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 1, . . . , FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.

摘要翻译： 使用NAND闪速存储器（MDY.X）的高速大容量存储装置适用于在实时条件下记录和重放视频数据流，其中数据在闪速存储器中被逐页地处理并被并行写入多个 内存总线（MBy）。 然而，对于使用多个独立数据流进行操作，需要显着的缓冲区大小。 根据本发明，来自不同数据流的数据被收集在相应的不同缓冲器（FIFO 1，...，FIFO Z）中，直到当前缓冲器中收集的数据量对应于当前数据块中的一个。 然后，将来自当前缓冲器的当前数据块的数据存储到连接到当前一个存储器总线的存储器中，其中相关数据流的后续缓冲数据块稍后被存储到连接到下一个存储器总线 存储器总线，相对于当前存储器总线的数量增加了以下存储器总线的数量。 重复这些步骤，对于使用缓冲器中的其他可用缓冲器和其它存储器总线的数据流中的其他步骤也是如此。 结合相应的缓冲区控制，可以以灵活的方式分配和使用最少数量的缓冲区。

公开(公告)号：US07613023B2

公开(公告)日：2009-11-03

申请号：US11887869

申请日：2006-02-21

申请人： Michael Drexler ,  Axel Kochale ,  Jens Peter Wittenburg

发明人： Michael Drexler ,  Axel Kochale ,  Jens Peter Wittenburg

IPC分类号： G11C5/06

CPC分类号： G06F13/4239

摘要： When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable connection and which is also able to be used for shots under difficult conditions, particularly action shots. The inventive memory arrangement involves the use of a number of non-volatile memory chips which are connected together with a favorable level of circuit complexity. To be able to cope with the high data rate for the incoming video and/or audio data, a plurality of parallel supply buses are provided. Each supply bus has an associated number of memory chips. In this case, the memory word length of the memory chips is greater than the bus width of a data/address bus. A supply bus with high-quality multiplexing has a respective associated number of demultiplexer/driver circuits which match the bus width of the supply bus to the memory word length of the memory chips. There are respectively as many downstream memory chips per demultiplexer/driver circuit as prescribed by a value X, the value X being limited by the memory technology used, namely by the maximum number of circuits which can be connected, also called the “fan-out” value. The memory chips used are preferably NAND Flash EPROM memory chips.

摘要翻译： 当使用数字视频记录器记录未压缩视频和/或音频数据时，需要基于非易失性集成电路的鲁棒存储器布置，其能够直接安装在摄像机上而不需要长的外部电缆连接， 这也能够用于在困难条件下拍摄，特别是动作镜头。 本发明的存储器装置涉及使用多个非易失性存储器芯片，它们以良好的电路复杂度连接在一起。 为了能够应付进入的视频和/或音频数据的高数据速率，提供了多个并行供应总线。 每个供电总线具有相关数量的存储器芯片。 在这种情况下，存储器芯片的存储器字长度大于数据/地址总线的总线宽度。 具有高质量复用的电源总线具有相应数量的解复用器/驱动器电路，其将供电总线的总线宽度与存储器芯片的存储器字长度相匹配。 分别由值X规定的每个解复用器/驱动器电路的下游存储器芯片分别是多少，值X受到所使用的存储器技术的限制，即由可连接的最大数量的电路，也称为“扇出 “价值。 所使用的存储器芯片优选地是NAND闪存EPROM存储器芯片。

公开(公告)号：US20070103214A1

公开(公告)日：2007-05-10

申请号：US11593738

申请日：2006-11-07

申请人： Michael Drexler ,  Ralf-Detlef Schaefer

发明人： Michael Drexler ,  Ralf-Detlef Schaefer

IPC分类号： H03L7/06

CPC分类号： H03L7/143 ,  H03L7/07 ,  H03L7/22

摘要： An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).

摘要翻译： 电子电路包括第一和第二PLL级（PLL 1，PLL 2），其可以根据PLL电路中的第一个锁定到输入信号（IN）并联或串联。 当并行地，只有第二PLL电路（PLL 2）正在向电子电路的输出主动地提供时钟信号。 第一个PLL电路（PLL 1）继续尝试锁定输入信号（IN）。 锁定检测器（LD）监视第一PLL电路（PLL 1）对输入信号（IN）的锁定状态，并且在锁定时，设置开关（S1，S2）以耦合第一PLL电路的输出 PLL 1）连接到第二PLL电路（PLL2）的输入，并将第二PLL电路（PLL 2）的输出耦合到第一PLL电路（PLL 1）的输入端。

公开(公告)号：US5982910A

公开(公告)日：1999-11-09

申请号：US604061

申请日：1996-02-20

申请人： Michael Drexler ,  Marco Winter

发明人： Michael Drexler ,  Marco Winter

IPC分类号： H04N7/32 ,  G06T7/20 ,  G06K9/00

CPC分类号： G06T7/2026 ,  G06T2207/10016

摘要： In the case of the storage or transmission of moving images, it is frequently necessary to reduce the large number of information items by means of suitable compression methods. In order to estimate the movement, the image to be coded is in this case split into blocks, and each of these reference blocks R is compared with blocks of the same size of the preceding image, and a movement information item is derived. Conventional methods for movement estimation in this case use all the pixels in the reference block R and in the search area S. Since this very complicated method requires very fast, and thus expensive, hardware, the so-called quincunx undersampling is applied to the search area S. In the case of the reference block R, one quincunx undersampled pixel is used for even parity of the movement vector and the other quincunx undersampled pixel is used for odd parity, depending on which position is being investigated. For the search area S, it is then necessary to store only half the pixels which are required for movement estimation. The memory requirement and the bandwidth of the memory are thus reduced by half.

摘要翻译： 在运动图像的存储或传输的情况下，通常需要通过适当的压缩方法来减少大量的信息。 为了估计运动，将要编码的图像在这种情况下被分割成块，并且将这些参考块R中的每一个与前一图像的大小相同的块进行比较，并导出运动信息项。 在这种情况下，传统的移动估计方法使用参考块R和搜索区域S中的所有像素。由于这种非常复杂的方法需要非常快速且因此昂贵的硬件，所以所谓的五次采样欠采样被应用于搜索 在参考块R的情况下，根据正在研究的位置，使用一个五次幂欠采样像素用于运动矢量的偶校验，而另一个五次采样欠采样像素用于奇校验。 对于搜索区域S，则仅需要存储运动估计所需的像素的一半。 因此，存储器需求和存储器的带宽减少了一半。