利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.02 秒)

    Pseudo-random address generation mechanism that reduces address translation time
    1.
    发明授权
    Pseudo-random address generation mechanism that reduces address translation time 失效
    伪随机地址生成机制，减少地址转换时间

    公开(公告)号：US5897662A

    公开(公告)日：1999-04-27

    申请号：US517759

    申请日：1995-08-18

    申请人： Michael Joseph Corrigan ,  Sheldon Bernard Levenstein ,  Terrence James Stewart

    发明人： Michael Joseph Corrigan ,  Sheldon Bernard Levenstein ,  Terrence James Stewart

    IPC分类号： G06F12/10 ,  G06F12/02

    CPC分类号： G06F12/1009

    摘要： It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), which, as mentioned, leads to increased address translation time because of clumping. The address allocation mechanism of the present invention reduces clumping by allocating virtual segment addresses in a pseudo-random order. This decreases the likelihood that virtual segment addresses that are allocated together end up in the same set or sets of virtual segment addresses within the address translation table.

    摘要翻译： 已知分配在一起的虚拟存储器段一起被一起使用。 使用现有的顺序地址分配机制，这又意味着程序倾向于最终使用相同的虚拟段地址集合（即，在相同的最小或最小值）中，如上所述，这些虚拟段地址导致增加地址转换时间，因为 凝结。 本发明的地址分配机制通过以伪随机顺序分配虚拟分段地址来减少分组。 这降低了分配在一起的虚拟分段地址在地址转换表中的相同集合或虚拟分段地址集合的可能性。

    Changing page size in storage media of computer system
    2.
    发明授权
    Changing page size in storage media of computer system 失效
    更改计算机系统存储介质中的页面大小

    公开(公告)号：US5765201A

    公开(公告)日：1998-06-09

    申请号：US509486

    申请日：1995-07-31

    申请人： Mark Gregory Manges ,  Lynn K. Chung ,  Shiun Lee ,  Arlys Jean Leitzen ,  Edwin Charles Grazier ,  Michael Joseph Corrigan ,  Mark Philip Piazza

    发明人： Mark Gregory Manges ,  Lynn K. Chung ,  Shiun Lee ,  Arlys Jean Leitzen ,  Edwin Charles Grazier ,  Michael Joseph Corrigan ,  Mark Philip Piazza

    IPC分类号： G06F3/06 ,  G06F12/10 ,  G06F12/02

    CPC分类号： G06F3/0607 ,  G06F12/10 ,  G06F3/0638 ,  G06F3/0676 ,  G06F2212/652

    摘要： When a computer system is upgraded, such as by adding a more advanced processor chip and/or a new operating system, a different page size may be employed. The page size is altered for data previously stored in a storage medium such as a hard disk in the computer system, without removing all of the data from the medium and rewriting it. Data is stored in the medium in blocks or sectors which have headers defining the block. Also, tables define memory objects and segments, and locate virtual memory addresses in physical memory. The headers and/or tables can be changed without rewriting all of the data in the sectors or pages in physical memory, so the page size is changed to accommodate the new system components, without excessive burden on system hardware or undue expenditure of time. In an example, in changing from a CISC processor with a 512-byte page size to a RISC system with a 4K-byte page size, the segments are changed to always be of a size of an integral multiple of 4K, and "extents" or subdivisions within a segment are changed to be multiples of 4K. Any excess space generated by these changes is zeroed. After alteration, the media (such as disks) can be accessed by either the CISC system or the new upgraded RISC system.

    摘要翻译： 当升级计算机系统时，例如通过添加更先进的处理器芯片和/或新的操作系统，可以采用不同的页面大小。 对于先前存储在诸如计算机系统中的硬盘的存储介质中的数据，页面大小被改变，而不从介质中移除所有数据并重写它。 数据被存储在具有定义块的头部的块或扇区中的介质中。 此外，表定义内存对象和段，并在物理内存中定位虚拟内存地址。 可以改变报头和/或表，而无需重写物理存储器中的扇区或页面中的所有数据，因此页面大小被改变以适应新的系统组件，而不会对系统硬件造成过度的负担或不适当的时间支出。 在一个例子中，在从具有512字节页面大小的CISC处理器更改为具有4K字节页面大小的RISC系统时，段被改变为总是4K的整数倍的大小，并且“范围” 或分段内的细分被改变为4K的倍数。 由这些更改生成的任何多余的空间归零。 更改后，可以通过CISC系统或新升级的RISC系统访问介质（如磁盘）。

    Task synchronization mechanism and method
    3.
    发明授权
    Task synchronization mechanism and method 有权
    任务同步机制和方法

    公开(公告)号：US06990560B2

    公开(公告)日：2006-01-24

    申请号：US10346010

    申请日：2003-01-16

    申请人： William Joseph Armstrong ,  Michael Joseph Corrigan ,  Gary Ross Ricard ,  Timothy Joseph Torzewski

    发明人： William Joseph Armstrong ,  Michael Joseph Corrigan ,  Gary Ross Ricard ,  Timothy Joseph Torzewski

    IPC分类号： G06F12/02

    CPC分类号： G06F9/526 ,  G06F9/544

    摘要： A task synchronization mechanism operates on a global lock that is shared between processors an on local locks that are not shared between processors. The local locks are processor-specific locks. Each processor-specific lock is dedicated to a particular processor in the system. When shared access to a resource is required, a processor updates its processor-specific lock to indicate the processor is sharing the resource. Because each processor-specific lock is dedicated to a particular processor, this eliminates a significant portion of the memory bus traffic associated with all processors reading and updating the same lock. When exclusive access to a resource is required, the requesting processor waits until the count of all processor-specific locks indicate that none of these processors have a lock on the resource. Once no processor has a lock on the resource, exclusive access to the resource may be granted.

    摘要翻译： 任务同步机制对在处理器之间共享的全局锁进行操作，本地锁在处理器之间未共享。 本地锁是处理器特定的锁。 每个处理器特定的锁专用于系统中的特定处理器。 当需要对资源的共享访问时，处理器更新其处理器特定的锁，以指示处理器正在共享资源。 因为每个特定于处理器的锁专用于特定的处理器，所以这消除了与所有处理器相关联的存储器总线流量的相当大部分读取和更新相同的锁。 当需要对资源的独占访问时，请求处理器等待直到所有特定于处理器的锁的计数指示这些处理器中没有一个对资源有锁定。 一旦没有处理器对资源进行锁定，就可以授予资源的独占访问权限。

    Interrupt handlers used in different modes of operations
    4.
    发明授权
    Interrupt handlers used in different modes of operations 失效
    中断处理程序用于不同的操作模式

    公开(公告)号：US06772259B2

    公开(公告)日：2004-08-03

    申请号：US09952852

    申请日：2001-09-12

    申请人： Michael Joseph Corrigan ,  David Robert Engebretsen

    发明人： Michael Joseph Corrigan ,  David Robert Engebretsen

    IPC分类号： G06F1324

    CPC分类号： G06F9/4812 ,  G06F13/24

    摘要： According to the present invention, when an interrupt occurs in a computer system running an operating system, control takes a separate code path in the operating system, depending on whether the computer system is in non-partitioned mode or partitioned mode, before converging to a common mode-independent interrupt handler that services the interrupt. Along each separate code path, hardware state of the computer system which is relevant to the processing of the interrupt is changed to a consistent hardware state so that the common mode-independent interrupt handler can run properly in both modes.

    摘要翻译： 根据本发明，当在运行操作系统的计算机系统中发生中断时，根据计算机系统是否处于非分区模式或分区模式，控制在操作系统中采用单独的代码路径，然后收敛到 共模独立的中断处理程序服务于中断。 沿着每个单独的代码路径，与处理中断相关的计算机系统的硬件状态被改变为一致的硬件状态，使得共模独立的中断处理程序能够以两种模式正常运行。

    Integrating multi-modal synchronous interrupt handlers for computer system
    5.
    发明授权
    Integrating multi-modal synchronous interrupt handlers for computer system 失效
    集成计算机系统的多模态同步中断处理程序

    公开(公告)号：US5734910A

    公开(公告)日：1998-03-31

    申请号：US577831

    申请日：1995-12-22

    申请人： Michael Joseph Corrigan ,  Steven Leonard Jones ,  Larry Wayne Loen ,  David Robert Russell, Jr. ,  Philip Braun Winterfield

    发明人： Michael Joseph Corrigan ,  Steven Leonard Jones ,  Larry Wayne Loen ,  David Robert Russell, Jr. ,  Philip Braun Winterfield

    IPC分类号： G06F9/46 ,  G06F9/48

    CPC分类号： G06F9/4812 ,  G06F9/463

    摘要： A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the "zeroth" level, is combined with a virtualized interrupt vector table. An identical zeroeth level handler is inserted at each of the processor's interrupt vector entry pints. These short code sequences are the first to gain control following an interrupt. They are handwritten in the platform's native instruction set to be mode-independent. For example, if the platform's processor does not alter the "endianness" of the machine state following an interrupt, the "zeroeth level" code must be written for endian neutrality; likewise, for 32/64-bit mode, etc. For each mode of operation, there is created a Virtualized Vector Table to represent the proper interrupt handlers for each physical interrupt level. Each task data structure, implicitly reflecting its unique mode of operation, contains a pointer to its virtualized vector table. The zeroeth-level handlers then extract the virtualized vector table reference for their own interrupt level and indirectly pass control to the preloaded table value.

    摘要翻译： 执行多种操作模式的处理系统的同步中断处理程序使用写入“第零”级执行的最少数量的中断处理程序代码与虚拟中断向量表组合。 每个处理器的中断向量入口品位都插入相同的零级处理器。 这些短代码序列是在中断之后首先获得控制的。 它们在平台的本机指令集中手写成与模式无关。 例如，如果平台的处理器不会在中断之后改变机器状态的“字节顺序”，则必须为端点中立写入“零级”代码; 同样，对于+ E，fra 32/64 + EE位模式等。对于每种操作模式，都创建了一个虚拟化向量表来表示每个物理中断级别的适当的中断处理程序。 每个任务数据结构，隐含地反映其唯一的操作模式，包含一个指向其虚拟向量表的指针。 零级处理程序然后提取虚拟化向量表引用自己的中断级别，并将控制间接地传递给预加载的表值。

    Mechanism that provides efficient multi-word load atomicity
    6.
    发明授权
    Mechanism that provides efficient multi-word load atomicity 失效
    提供有效的多字负载原子性的机制

    公开(公告)号：US07296120B2

    公开(公告)日：2007-11-13

    申请号：US10992436

    申请日：2004-11-18

    申请人： Michael Joseph Corrigan ,  Timothy Joseph Torzewski

    发明人： Michael Joseph Corrigan ,  Timothy Joseph Torzewski

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

    摘要： Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

    摘要翻译： 公开了一种在不引起额外的存储器利用的情况下提供原子，多字负载支持的装置，方法和程序产品。 双字是原子加载的，而不使用一个或多个附加字段而不使用锁。 结合高速缓存未命中时使用无效标记来确定加载的双字是否已被原子地存储和加载，因此是有效的。

    Apparatus and method for controlling access to software
    8.
    发明授权
    Apparatus and method for controlling access to software 失效
    用于控制软件访问的装置和方法

    公开(公告)号：US5933497A

    公开(公告)日：1999-08-03

    申请号：US11042

    申请日：1993-01-29

    申请人： Robert Carl Beetcher ,  Michael Joseph Corrigan ,  Francis Joseph Reardon, Jr. ,  James William Moran

    发明人： Robert Carl Beetcher ,  Michael Joseph Corrigan ,  Francis Joseph Reardon, Jr. ,  James William Moran

    IPC分类号： G06F21/22 ,  G06F1/00 ,  G06F9/445 ,  G06F21/00 ,  H04L9/00

    CPC分类号： G06F21/121

    摘要： Software is distributed without entitlement to run, while a separately distributed encrypted entitlement key enables execution of the software. The key includes the serial number of the computer for which the software is licensed, together with a plurality of entitlement bits indicating which software modules are entitled to run on the machine. A secure decryption mechanism contained on the computer fetches its serial number and uses it as a key to decrypt the entitlement information, which is then stored in a product lock table in memory. The distributed software contains a plurality of entitlement verification triggers. Each trigger is a single machine instruction in the object code, identifying a product number of the software module. When a trigger is encountered during execution, the computer checks the product lock table entry corresponding to the product number of the software. If the product is entitled to run, execution continues normally; otherwise execution is aborted. Because this verification involves only a single machine instruction, it can be done with virtually no impact to overall system performance. As a result, it is possible to place a substantial number of such entitlement verification triggers in the object code, making it virtually impossible for someone to alter the code by "patching" the triggers. The triggering instruction may alternatively perform some useful work in parallel with entitlement verification.

    摘要翻译： 软件分发无权运行，而单独分发的加密授权密钥可以执行软件。 密钥包括软件许可的计算机的序列号，以及指示哪些软件模块有权在机器上运行的多个授权位。 包含在计算机上的安全解密机制提取其序列号并将其用作解密权利信息的密钥，然后存储在存储器中的产品锁定表中。 分布式软件包含多个授权验证触发器。 每个触发器是目标代码中的单个机器指令，标识软件模块的产品编号。 在执行期间遇到触发器时，计算机将检查与软件产品编号对应的产品锁定表项。 如果产品有权运行，执行继续正常; 否则执行中止。 因为该验证仅涉及单个机器指令，所以可以对整个系统性能几乎没有影响。 因此，可以将大量这样的授权验证触发器放置在目标代码中，使得几乎不可能通过“修补”触发器来改变代码。 触发指令也可以与授权验证并行地执行一些有用的工作。

    Mechanism that provides efficient multi-word load atomicity
    9.
    发明授权
    Mechanism that provides efficient multi-word load atomicity 失效
    提供有效的多字负载原子性的机制

    公开(公告)号：US07873794B2

    公开(公告)日：2011-01-18

    申请号：US11842335

    申请日：2007-08-21

    申请人： Michael Joseph Corrigan ,  Timothy Joseph Torzewski

    发明人： Michael Joseph Corrigan ,  Timothy Joseph Torzewski

    IPC分类号： G06F13/00

    CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

    摘要： Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

    摘要翻译： 公开了一种在不引起额外的存储器利用的情况下提供原子，多字负载支持的装置，方法和程序产品。 双字是原子加载的，而不使用一个或多个附加字段而不使用锁。 结合高速缓存未命中时使用无效标记来确定加载的双字是否已被原子地存储和加载，因此是有效的。