公开(公告)号：US06691146B1

公开(公告)日：2004-02-10

申请号：US09314214

申请日：1999-05-19

申请人： Troy David Armstrong ,  William Joseph Armstrong ,  Michael Joseph Corrigan ,  Naresh Nayar ,  Thomas Rembert Sand ,  Jeffrey Jay Scheel ,  Erik Tkal ,  Kenneth Charles Vossen

发明人： Troy David Armstrong ,  William Joseph Armstrong ,  Michael Joseph Corrigan ,  Naresh Nayar ,  Thomas Rembert Sand ,  Jeffrey Jay Scheel ,  Erik Tkal ,  Kenneth Charles Vossen

IPC分类号： G06F900

CPC分类号： G06F9/45537

摘要： A partition manager for managing logical partitions in a computer system includes hooks to low-level operating system code in one of the logical partitions. By using the operating system code to manage the resources of a computer system, any changes that are made to the operating system are automatically reflected in the function of the partition manager. In addition, low-level functions of operating systems, which are often well-debugged and tested, can be used when generating a new partition manager, greatly simplifying the time and reducing the cost of producing a partition manager.

摘要翻译： 用于管理计算机系统中的逻辑分区的分区管理器包括到逻辑分区之一中的低级操作系统代码的钩子。 通过使用操作系统代码来管理计算机系统的资源，对操作系统进行的任何更改将自动反映在分区管理器的功能中。 此外，在生成新的分区管理器时，可以使用经常进行良好调试和测试的操作系统的低级功能，大大简化了时间并降低了生成分区管理器的成本。

公开(公告)号：US6085277A

公开(公告)日：2000-07-04

申请号：US950755

申请日：1997-10-15

申请人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  William Joseph Armstrong ,  Thomas Rembert Sand

发明人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  William Joseph Armstrong ,  Thomas Rembert Sand

IPC分类号： G06F9/46 ,  G06F13/00

CPC分类号： G06F9/546

摘要： An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.

摘要翻译： 中断和消息批处理设备和方法通过将I / O完成事件与单个处理器中断分组，以使I / O操作等待时间要求与处理器利用率要求平衡来优化，从而减少处理器中断和结果上下文切换的数量和频率 整体计算机系统性能。 本发明在I / O总线上从处理器复合体向I / O适配器发送消息，命令连接到I / O适配器的I / O设备执行功能。 完成命令功能后，I / O适配器中的消息处理器会生成一条消息，并将其发送到I / O总线上的处理器复合体。 该消息在存储器的消息队列中排队，消息计数被更新，并且当消息计数超过消息步调计数时以及何时发送处理器复杂中断。 如果消息具有相对较高的延迟，或者如果消息具有相对低的延迟，则信令定时器也可以被编程为具有快速的响应时间值。 当消息排入队列时，启动信令定时器，然后当消息计数超过消息起搏计数或信令定时器过去时，信号通知处理器复杂中断。

公开(公告)号：US06986017B2

公开(公告)日：2006-01-10

申请号：US10422215

申请日：2003-04-24

申请人： Travis James Pizel ,  Thomas Rembert Sand ,  William Alan Thompson

发明人： Travis James Pizel ,  Thomas Rembert Sand ,  William Alan Thompson

IPC分类号： G06F12/00

CPC分类号： G06F12/1475 ,  G06F12/109 ,  H04L47/10 ,  H04L47/18 ,  H04L47/39

摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment pre-register buffers remotely and create tokens locally that represent the buffers prior to a data transfer operation that uses the tokens to access the buffers. In an embodiment, the buffers are pre-registered via a translation table, and the tokens are used as an offset into the translation table. In an embodiment, the pre-registration verifies that the buffer is within memory allocated to a logical partition, which protects against the risk of address corruption.

摘要翻译： 一种方法，装置，系统和信号承载介质，其在一个实施例中预先寄存缓冲器，并且在使用令牌访问缓冲器的数据传送操作之前本地创建代表缓冲器的令牌。 在一个实施例中，缓冲器经由转换表预先登记，并且令牌被用作到转换表中的偏移量。 在一个实施例中，预注册验证缓冲器在分配给逻辑分区的存储器内，其防止地址损坏的风险。

公开(公告)号：US06275876B1

公开(公告)日：2001-08-14

申请号：US09316243

申请日：1999-05-21

申请人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

发明人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

IPC分类号： G06F1312

CPC分类号： G06F13/126

摘要： A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

摘要翻译： 计算系统包括处理系统，至少第一寄存器和控制系统。 处理系统产生第一指令集和第一地址，用于存储第一指令集的第一完成状态。 第一个寄存器从处理系统接收第一个地址。 控制系统将从处理系统接收的第一指令集传送到外部设备。 控制系统从外部设备接收第一完成状态，访问第一寄存器以确定第一指令集的第一地址，并将第一完成状态存储在所确定的第一地址中。

公开(公告)号：US07088715B2

公开(公告)日：2006-08-08

申请号：US10933598

申请日：2004-09-03

申请人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Micheal Valk

发明人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Micheal Valk

IPC分类号： H04L12/28

CPC分类号： H04L49/351 ,  H04L49/3009

摘要： A method and system for communication in a system area network (SAN) data processing system are described. The SAN includes a plurality of interconnected nodes that each have at least one port for communication. To avoid communication-induced errors that may arise, for example, if multiple nodes share the same node ID, the port of a node in the SAN is marked as “fenced” to prevent transmission of packets of a first traffic type while permitting transmission of packets of a second traffic type. The marking of the port may be recorded, for example, in a configuration register of the port. While the port is fenced, only packets of other than the first traffic type are routed via the port. In one preferred embodiment, the second traffic type represents SAN configuration traffic, and the first traffic type represents non-configuration traffic. In this preferred embodiment, the marking of the port may be removed following communication of configuration traffic utilized to negotiate unique node ID throughout the SAN.

摘要翻译： 描述了系统区域网（SAN）数据处理系统中的通信方法和系统。 SAN包括多个互连的节点，每个节点具有至少一个用于通信的端口。 为了避免可能出现的通信引起的错误，例如，如果多个节点共享相同的节点ID，则SAN中的节点的端口被标记为“围栏”，以防止第一业务类型的分组的传输，同时允许 第二种流量类型的数据包。 端口的标记可以记录在例如端口的配置寄存器中。 当端口被隔离时，只有除第一个流量类型之外的数据包通过端口路由。 在一个优选实施例中，第二流量类型表示SAN配置流量，第一流量类型表示非配置流量。 在该优选实施例中，可以在通过用于在整个SAN中协商唯一节点ID的配置流量通信之后去除端口的标记。

公开(公告)号：US06944155B2

公开(公告)日：2005-09-13

申请号：US09800398

申请日：2001-03-05

申请人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Micheal Valk

发明人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Micheal Valk

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L49/351 ,  H04L49/3009

摘要： A method and system for communication in a system area network (SAN) data processing system are described. The SAN includes a plurality of interconnected nodes that each have at least one port for communication. To avoid communication-induced errors that may arise, for example, if multiple nodes share the same node ID, the port of a node in the SAN is marked as “fenced” to prevent transmission of packets of a first traffic type while permitting transmission of packets of a second traffic type. The marking of the port may be recorded, for example, in a configuration register of the port. While the port is fenced, only packets of other than the first traffic type are routed via the port. In one preferred embodiment, the second traffic type represents SAN configuration traffic, and the first traffic type represents non-configuration traffic. In this preferred embodiment, the marking of the port may be removed following communication of configuration traffic utilized to negotiate unique node ID throughout the SAN.

摘要翻译： 描述了系统区域网（SAN）数据处理系统中的通信方法和系统。 SAN包括多个互连的节点，每个节点具有至少一个用于通信的端口。 为了避免可能出现的通信引起的错误，例如，如果多个节点共享相同的节点ID，则SAN中的节点的端口被标记为“围栏”，以防止第一业务类型的分组的传输，同时允许 第二种流量类型的数据包。 端口的标记可以记录在例如端口的配置寄存器中。 当端口被隔离时，只有除第一个流量类型之外的数据包通过端口路由。 在一个优选实施例中，第二流量类型表示SAN配置流量，第一流量类型表示非配置流量。 在该优选实施例中，可以在通过用于在整个SAN中协商唯一节点ID的配置流量通信之后去除端口的标记。

公开(公告)号：US20100082853A1

公开(公告)日：2010-04-01

申请号：US12240059

申请日：2008-09-29

申请人： Timothy Roy Block ,  Thomas Rembert Sand ,  Timothy Jerry Schimke

发明人： Timothy Roy Block ,  Thomas Rembert Sand ,  Timothy Jerry Schimke

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/409 ,  G06F13/387

摘要： A method and apparatus are provided for implementing system to system communication in a switchless non-InfiniBand (IB) compliant environment. IB architected multicast facilities are used to communicate between HCAs in a loop or string topology. Multiple HCAs in the network subscribe to a predetermined multicast address. Multicast messages sent by one HCA destined to the pre-determined multicast address are received by other HCAs in the network. Intermediate TCA hardware, per IB architected multicast support, forward the multicast messages on via hardware facilities, which do not require invocation of software facilities thereby providing performance efficiencies. The messages flow until picked up by an HCA on the network. Architected higher level IB connections, such as IB supported Reliable Connections (RCs) are established using the multicast message flow, eliminating the need for an IB Subnet Manager (SM).

摘要翻译： 提供了一种用于在不涉及非InfiniBand（IB）兼容环境中实现系统到系统通信的方法和装置。 IB架构的多播设备用于以循环或串联拓扑结构在HCA之间进行通信。 网络中的多个HCA订阅预定的多播地址。 一个HCA发送到预定的多播地址的组播消息由网络中的其他HCA接收。 中间TCA硬件，根据IB架构的组播支持，通过硬件设施转发组播消息，不需要调用软件设施，从而提供性能效率。 消息流向网络上的HCA接收。 建立的更高级别的IB连接（如IB支持的可靠连接（RC））使用多播消息流建立，从而无需IB子网管理器（SM）。

公开(公告)号：US07676623B2

公开(公告)日：2010-03-09

申请号：US11610638

申请日：2006-12-14

申请人： Mark Edward Fisher ,  Charles Scott Graham ,  Kris Marie Kendall ,  Thomas Rembert Sand ,  Timothy Jerry Schimke

发明人： Mark Edward Fisher ,  Charles Scott Graham ,  Kris Marie Kendall ,  Thomas Rembert Sand ,  Timothy Jerry Schimke

IPC分类号： G06F13/20

CPC分类号： H04L41/0869 ,  H04L41/12

摘要： Methods and systems for discovering whether a given connection to an InfiniBand port is a standard InfiniBand connection or a non-standard connection (e.g., indicating the presence of a proprietary device) are provided. The discovery may be performed by an end node, such that the end node interoperates with all standard InfiniBand components. Specific actions that are vendor unique, and potentially not compliant with the InfiniBand architecture, may not be done until after the discovery is complete and it has been verified that the noncompliant action will only be directed to entities know to be capable of processing them. These actions may include assuming the configuration responsibilities that would have been performed by the Subnet Manager in a standard InfiniBand network.

摘要翻译： 用于发现与InfiniBand端口的给定连接是否为标准InfiniBand连接或非标准连接（例如，指示专有设备的存在）的方法和系统。 发现可以由终端节点执行，使得终端节点与所有标准InfiniBand组件互操作。 供应商唯一的，可能不符合InfiniBand体系结构的具体操作可能在发现完成后才能完成，并且已经验证了不合规的操作将仅针对知道能够处理它们的实体。 这些操作可能包括假定由Subnet Manager在标准InfiniBand网络中执行的配置职责。

公开(公告)号：US07653769B2

公开(公告)日：2010-01-26

申请号：US11610634

申请日：2006-12-14

申请人： Mark Edward Fisher ,  Charles Scott Graham ,  Thomas Rembert Sand

发明人： Mark Edward Fisher ,  Charles Scott Graham ,  Thomas Rembert Sand

IPC分类号： G06F13/00

CPC分类号： C07K14/811 ,  A61K48/005 ,  A61K48/0075 ,  C07K14/71 ,  C12N2799/022 ,  H04L45/02 ,  H04L49/355 ,  H04L49/358

摘要： Methods and systems for discovering and managing devices connected to InfiniBand ports are provided. The discovery may be performed by an end node, such that the end node interoperates with all standard InfiniBand components. Specific actions that are vendor unique, and potentially not compliant with the InfiniBand architecture, may not be done until after the discovery is complete and it has been verified that the noncompliant action will only be directed to entities known to be capable of processing them. These actions may include assuming the configuration responsibilities that would have been performed by the Subnet Manager in a standard InfiniBand network.

摘要翻译： 提供了用于发现和管理连接到InfiniBand端口的设备的方法和系统。 发现可以由终端节点执行，使得终端节点与所有标准InfiniBand组件互操作。 供应商唯一的，可能不符合InfiniBand体系结构的具体操作可能不会在发现完成后才能完成，并且已经验证不合规的操作将仅针对已知能够处理它们的实体。 这些操作可能包括假定由Subnet Manager在标准InfiniBand网络中执行的配置职责。

公开(公告)号：US6073253A

公开(公告)日：2000-06-06

申请号：US995075

申请日：1997-12-19

申请人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Paul John Johnsen ,  Thomas Rembert Sand

发明人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Paul John Johnsen ,  Thomas Rembert Sand

IPC分类号： G06F1/24 ,  G06F11/267 ,  G06F11/00

CPC分类号： G06F11/267 ,  G06F1/24

摘要： An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state. Each of these reset states is well-defined and has the advantage of predictable behavior during and after execution of the corresponding reset procedure. A built-in self-test procedure is also defined that sequentially examines each function associated within a multifunction device connected to the local bus to coordinate the initiation, execution and completion of built in self-tests.

摘要翻译： 允许各种复位过程和相应复位状态的装置，系统和方法。 为单个功能或多功能设备中的每个I / O设备适配器提供器件复位控制寄存器。 器件复位控制寄存器允许对单个功能器件，多功能器件作为一个整体进行更大程度的控制，以及多功能器件中的各个器件功能。 设备立即状态寄存器可以同步各种复位过程。 逻辑上电复位程序，有向单元复位程序和定向接口复位程序利用设备复位控制寄存器提供的更大程度的控制力将I / O设备适配器，单功能设备或多功能设备强制为相应的逻辑 上电复位状态，定向单元复位状态或定向接口复位状态。 这些复位状态中的每一个都被明确定义，并且具有在执行相应的复位过程期间和之后可预测的行为的优点。 还定义了一个内置的自检程序，依次检查连接到本地总线的多功能设备中相关联的每个功能，以协调内置自检的启动，执行和完成。