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1.发明授权System for communicating command parameters between a processor and a memory flow controller 失效用于在处理器和存储器流控制器之间传送命令参数的系统公开(公告)号：US08024489B2
公开(公告)日：2011-09-20
申请号：US12106483
申请日：2008-04-21
IPC分类号： G06F3/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统。 该系统利用通道接口作为在处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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2.发明申请System for Communicating Command Parameters Between a Processor and a Memory Flow Controller 失效用于在处理器和内存流控制器之间通信命令参数的系统公开(公告)号：US20080244200A1
公开(公告)日：2008-10-02
申请号：US12106483
申请日：2008-04-21
IPC分类号： G06F12/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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3.发明授权System and method for communicating command parameters between a processor and a memory flow controller 失效用于在处理器和存储器流控制器之间传送命令参数的系统和方法公开(公告)号：US07386636B2
公开(公告)日：2008-06-10
申请号：US11207986
申请日：2005-08-19
IPC分类号： G06F3/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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4.发明授权Method for communicating instructions and data between a processor and external devices 失效在处理器和外部设备之间传送指令和数据的方法公开(公告)号：US07778271B2
公开(公告)日：2010-08-17
申请号：US11207970
申请日：2005-08-19
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的方法。 该方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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5.发明申请公开(公告)号：US20080288757A1
公开(公告)日：2008-11-20
申请号：US12129114
申请日：2008-05-29
IPC分类号： G06F9/38
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的机制。 该机制利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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6.发明授权公开(公告)号：US07869459B2
公开(公告)日：2011-01-11
申请号：US12129114
申请日：2008-05-29
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的机制。 该机制利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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7.发明申请SYSTEM AND METHOD FOR HANDLING MULTIPLE ALIASED SHADOW REGISTER NUMBERS TO ENHANCE LOCK ACQUISITION 审中-公开用于处理多个被遮挡的阴影寄存器编号的系统和方法以增加锁定采集公开(公告)号：US20080162823A1
公开(公告)日：2008-07-03
申请号：US11619033
申请日：2007-01-02
申请人： Michael N. Day , Charles R. Johns , Roy M. Kim , Peichun P. Liu
发明人： Michael N. Day , Charles R. Johns , Roy M. Kim , Peichun P. Liu
CPC分类号： G06F9/30087 , G06F9/30116 , G06F12/0815 , Y02D10/13
摘要： Exemplary embodiments include a method for enhancing lock acquisition in a multiprocessor system, the method including: sending a lock-load instruction from a first processor to a cache; setting a reservation flag for the first processor, storing a reservation address, storing a shadow register number, and sending lock data to the first processor in response to the lock-load instruction; placing the lock data in target and shadow registers of the first processor; determining from the lock data whether lock is taken; resending the lock-load instruction from the first processor to the cache upon a determination that the lock is taken; determining whether the reservation flag is still set and its main memory address and shadow register number match with the saved reservation address and shadow register number for the first processor; sending a status-quo signal to the first processor without resending the lock data to the first processor upon a determination that the reservation flag is still set for the first processor; and copying the lock data from the associated shadow register to the target register in response to the status-quo signal.
摘要翻译： 示例性实施例包括用于增强多处理器系统中的锁获取的方法，所述方法包括：将锁定加载指令从第一处理器发送到高速缓存; 设置第一处理器的预约标志，存储预约地址，存储影子寄存器号码，以及响应于锁定加载指令向第一处理器发送锁定数据; 将锁定数据放置在第一处理器的目标和影子寄存器中; 从锁定数据确定是否采取锁定; 在确定锁定时，将锁定加载指令从第一处理器重新发送到高速缓存; 确定保留标志是否仍然设置，并且其主存储器地址和影子寄存器号码与第一处理器的保存的预留地址和影子寄存器号码相匹配; 在确定所述预留标志仍然被设置用于所述第一处理器时，向所述第一处理器发送状态信号而不将所述锁定数据重新发送到所述第一处理器; 并且响应于状态信号将锁定数据从相关联的影子寄存器复制到目标寄存器。
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公开(公告)号：US20090217300A1
公开(公告)日：2009-08-27
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于与处理器事件设施进行通信的系统和方法。 系统和方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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公开(公告)号：US07500039B2
公开(公告)日：2009-03-03
申请号：US11207971
申请日：2005-08-19
CPC分类号： G06F13/24
摘要： A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种与处理器事件设施通信的方法。 该方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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10.发明授权公开(公告)号：US07930457B2
公开(公告)日：2011-04-19
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了与处理器事件设施通信的机制。 这些机制使用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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