公开(公告)号：US20080162823A1

公开(公告)日：2008-07-03

申请号：US11619033

申请日：2007-01-02

申请人： Michael N. Day ,  Charles R. Johns ,  Roy M. Kim ,  Peichun P. Liu

发明人： Michael N. Day ,  Charles R. Johns ,  Roy M. Kim ,  Peichun P. Liu

IPC分类号： G06F12/14 ,  G06F12/08

CPC分类号： G06F9/30087 ,  G06F9/30116 ,  G06F12/0815 ,  Y02D10/13

摘要： Exemplary embodiments include a method for enhancing lock acquisition in a multiprocessor system, the method including: sending a lock-load instruction from a first processor to a cache; setting a reservation flag for the first processor, storing a reservation address, storing a shadow register number, and sending lock data to the first processor in response to the lock-load instruction; placing the lock data in target and shadow registers of the first processor; determining from the lock data whether lock is taken; resending the lock-load instruction from the first processor to the cache upon a determination that the lock is taken; determining whether the reservation flag is still set and its main memory address and shadow register number match with the saved reservation address and shadow register number for the first processor; sending a status-quo signal to the first processor without resending the lock data to the first processor upon a determination that the reservation flag is still set for the first processor; and copying the lock data from the associated shadow register to the target register in response to the status-quo signal.

摘要翻译： 示例性实施例包括用于增强多处理器系统中的锁获取的方法，所述方法包括：将锁定加载指令从第一处理器发送到高速缓存; 设置第一处理器的预约标志，存储预约地址，存储影子寄存器号码，以及响应于锁定加载指令向第一处理器发送锁定数据; 将锁定数据放置在第一处理器的目标和影子寄存器中; 从锁定数据确定是否采取锁定; 在确定锁定时，将锁定加载指令从第一处理器重新发送到高速缓存; 确定保留标志是否仍然设置，并且其主存储器地址和影子寄存器号码与第一处理器的保存的预留地址和影子寄存器号码相匹配; 在确定所述预留标志仍然被设置用于所述第一处理器时，向所述第一处理器发送状态信号而不将所述锁定数据重新发送到所述第一处理器; 并且响应于状态信号将锁定数据从相关联的影子寄存器复制到目标寄存器。

公开(公告)号：US08024489B2

公开(公告)日：2011-09-20

申请号：US12106483

申请日：2008-04-21

申请人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

发明人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

IPC分类号： G06F3/00

CPC分类号： G06F13/32 ,  G06F13/1642

摘要： A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统。 该系统利用通道接口作为在处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US20080244200A1

公开(公告)日：2008-10-02

申请号：US12106483

申请日：2008-04-21

申请人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

发明人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

IPC分类号： G06F12/00

CPC分类号： G06F13/32 ,  G06F13/1642

摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US07386636B2

公开(公告)日：2008-06-10

申请号：US11207986

申请日：2005-08-19

申请人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

发明人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

IPC分类号： G06F3/00

CPC分类号： G06F13/32 ,  G06F13/1642

摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US20080071955A1

公开(公告)日：2008-03-20

申请号：US11532987

申请日：2006-09-19

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/36

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活锁状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US07861022B2

公开(公告)日：2010-12-28

申请号：US12393469

申请日：2009-02-26

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/36 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US20090164682A1

公开(公告)日：2009-06-25

申请号：US12393469

申请日：2009-02-26

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F12/00

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US07500035B2

公开(公告)日：2009-03-03

申请号：US11532987

申请日：2006-09-19

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/36 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US08171448B2

公开(公告)日：2012-05-01

申请号：US12129777

申请日：2008-05-30

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F17/50

CPC分类号： G06F11/0757

摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了一种用于动态锁分辨率电路的设计结构。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US20080228974A1

公开(公告)日：2008-09-18

申请号：US12129777

申请日：2008-05-30

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/00

CPC分类号： G06F11/0757

摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了一种用于动态锁分辨率电路的设计结构。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。