公开(公告)号：US08510512B2

公开(公告)日：2013-08-13

申请号：US12545246

申请日：2009-08-21

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

公开(公告)号：US07797600B2

公开(公告)日：2010-09-14

申请号：US12139114

申请日：2008-06-13

申请人： Louis B. Bushard ,  Nathan P. Chelstrom ,  Naoki Kiryu ,  David J. Krolak

发明人： Louis B. Bushard ,  Nathan P. Chelstrom ,  Naoki Kiryu ,  David J. Krolak

IPC分类号： G01R31/28

CPC分类号： G01R31/318525 ,  G01R31/3187

摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

摘要翻译： 一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。 逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。 响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。 响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。 执行非扫描锁存器环中的逻辑路径。 非扫描锁存器是逻辑路径的一部分。 从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

公开(公告)号：US20080228974A1

公开(公告)日：2008-09-18

申请号：US12129777

申请日：2008-05-30

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/00

CPC分类号： G06F11/0757

摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了一种用于动态锁分辨率电路的设计结构。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US4888773A

公开(公告)日：1989-12-19

申请号：US206757

申请日：1988-06-15

申请人： David L. Arlington ,  Jacqueline M. Cole ,  Bruce G. Hazelzet ,  David J. Krolak ,  Hehching H. Li ,  Bharat J. Oza ,  A. Frank Weaver

发明人： David L. Arlington ,  Jacqueline M. Cole ,  Bruce G. Hazelzet ,  David J. Krolak ,  Hehching H. Li ,  Bharat J. Oza ,  A. Frank Weaver

IPC分类号： G06F12/16 ,  G06F11/10 ,  G06F12/06

CPC分类号： G06F11/106 ,  G06F11/1028 ,  G06F11/1056

摘要： A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide seminconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

公开(公告)号：US20110047352A1

公开(公告)日：2011-02-24

申请号：US12545246

申请日：2009-08-21

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F15/76 ,  G06F9/02 ,  G06F12/08

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

摘要翻译： 数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。 第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于 第二处理节点。 第二处理节点包括具有目录的节点接口。 第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功 目录指示除第二处理节点之外的请求的目标存储块被缓存。

公开(公告)号：US07861022B2

公开(公告)日：2010-12-28

申请号：US12393469

申请日：2009-02-26

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/36 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US08504779B2

公开(公告)日：2013-08-06

申请号：US13445010

申请日：2012-04-12

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

摘要翻译： 数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。 第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于 第二处理节点。 第二处理节点包括具有目录的节点接口。 第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功 目录指示除第二处理节点之外的请求的目标存储块被缓存。

公开(公告)号：US08171448B2

公开(公告)日：2012-05-01

申请号：US12129777

申请日：2008-05-30

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F17/50

CPC分类号： G06F11/0757

摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了一种用于动态锁分辨率电路的设计结构。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。

公开(公告)号：US20120203976A1

公开(公告)日：2012-08-09

申请号：US13445010

申请日：2012-04-12

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

摘要翻译： 数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。 第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于 第二处理节点。 第二处理节点包括具有目录的节点接口。 第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功 目录指示除第二处理节点之外的请求的目标存储块被缓存。

公开(公告)号：US20080071955A1

公开(公告)日：2008-03-20

申请号：US11532987

申请日：2006-09-19

申请人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

发明人： Charles R. Johns ,  David J. Krolak ,  Peichun P. Liu ,  Alvan W. Ng

IPC分类号： G06F13/36

CPC分类号： G06F11/362 ,  G06F11/0724 ,  G06F11/0757

摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

摘要翻译： 提供了用于解决多处理器数据处理系统中的活锁状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。