公开(公告)号：US4646254A

公开(公告)日：1987-02-24

申请号：US892453

申请日：1986-08-04

申请人： Michael O'Connor ,  Randall L. Jackson ,  David P. Marple

发明人： Michael O'Connor ,  Randall L. Jackson ,  David P. Marple

IPC分类号： G01R23/15 ,  H04B15/00 ,  G06F15/20 ,  G06G7/19

CPC分类号： G01R23/15

摘要： A noise threshold estimating method for use in a high signal density environment defines a noise threshold level for a plurality of frequency divided channels such that X number of said channels will be defined as being active channels and the remaining channels as being inactive. Using a novel closed loop feedback technique to define a noise threshold level, the noise threshold estimator first compares the signal level of each incoming channel with an analog threshold voltage. A logic device counts the number of active channels and then scales that number according to a predetermined scaling function. The scaled binary number is added with the noise threshold level from the previous clocked interval to define a new noise threshold level. This binary noise threshold level is converted into an analog voltage and feedback to the feedback input of the noise comparison devices to be compared with the signal level of each incoming channel.

摘要翻译： 在高信号密度环境中使用的噪声阈值估计方法为多个分频信道定义噪声阈值电平，使得X个所述信道将被定义为活动信道，而剩余信道为非活动信道。 使用新颖的闭环反馈技术来定义噪声阈值电平，噪声阈值估计器首先将每个输入信道的信号电平与模拟阈值电压进行比较。 逻辑设备对活动通道的数量进行计数，然后根据预定的缩放功能对该数量进行缩放。 缩放的二进制数加上来自上一个时钟间隔的噪声阈值电平，以定义新的噪声阈值电平。 该二进制噪声阈值电平被转换为模拟电压并反馈到噪声比较装置的反馈输入端，以与每个输入信道的信号电平进行比较。

公开(公告)号：US4635217A

公开(公告)日：1987-01-06

申请号：US659055

申请日：1984-10-09

申请人： Michael O'Connor ,  Randall L. Jackson ,  David P. Marple

发明人： Michael O'Connor ,  Randall L. Jackson ,  David P. Marple

IPC分类号： H04B1/10 ,  G06F15/20 ,  G06G7/19

CPC分类号： H04B1/10

摘要： A noise threshold estimator for use in a high signal density environment defines a noise threshold level for a plurality of frequency divided channels such that X number of said channels will be defined as being active channels and the remaining channels as being inactive. Using a novel closed loop feedback technique to define a noise threshold level, the noise threshold estimator first compares the signal level of each incoming channel with an analog threshold voltage. A logic device counts the number of active channels and then scales that number according to a predetermined scaling function. The scaled binary number is added with the noise threshold level from the previous clocked interval to define a new noise threshold level. This binary noise threshold level is converted into an analog voltage and fedback to the feedback input of the noise comparison devices to be compared with the signal level of each incoming channel.

摘要翻译： 用于高信号密度环境的噪声阈值估计器定义了多个分频信道的噪声阈值电平，使得X个所述信道将被定义为活动信道，而其余信道被定义为非活动信道。 使用新颖的闭环反馈技术来定义噪声阈值电平，噪声阈值估计器首先将每个输入信道的信号电平与模拟阈值电压进行比较。 逻辑设备对活动通道的数量进行计数，然后根据预定的缩放功能对该数量进行缩放。 缩放的二进制数加上来自上一个时钟间隔的噪声阈值电平，以定义新的噪声阈值电平。 该二进制噪声阈值电平被转换为模拟电压并反馈到噪声比较装置的反馈输入，以与每个输入信道的信号电平进行比较。

公开(公告)号：US5754826A

公开(公告)日：1998-05-19

申请号：US511172

申请日：1995-08-04

申请人： Abbas El Gamal ,  David P. Marple ,  Justin M. Reyneri

发明人： Abbas El Gamal ,  David P. Marple ,  Justin M. Reyneri

IPC分类号： G06F17/50 ,  H01L21/70

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

摘要翻译： 使用本发明，仅需要对使用多种不同制造工艺制造的IC进行单一的设计和开发过程。 在该过程的一个实施例中，IC首先在使用通用的基于单元的架构（CBA）库的CAD系统上设计。 该通用CBA库代表用于不同进程技术的多个库。 然后使用最佳和最差情况的时序延迟以及从各种技术的组合导出的其他参数来模拟和验证所得通用设计。 因此，只需要创建和模拟一个设计。 然后通用设计规则和寄生参数用于优化通用设计的布局和路由。 然后使用由技术的组合确定的性能特征来模拟和验证后布局通用设计。 然后，接受的通用后布图设计移植到每个预期的制造工艺，以创建与每个制造工艺相关联的掩模图案。

公开(公告)号：US5777887A

公开(公告)日：1998-07-07

申请号：US439675

申请日：1995-05-12

申请人： David P. Marple ,  Laurence H. Cooke

发明人： David P. Marple ,  Laurence H. Cooke

IPC分类号： G06F11/20 ,  H03K19/177 ,  H04B17/00

CPC分类号： H03K19/17704 ,  H03K19/17764

摘要： An FPGA includes primary resources and redundant resources. To program an FPGA to perform a desired function, a pattern of programmable elements to be programmed that takes advantage of primary resources only is first prepared. This pattern is then modified responsive to previously obtained information about defects within the FPGA. The modified pattern takes advantage of redundant resources as direct or indirect substitutes for FPGA elements rendered unusable by defects. The FPGA is programmed in accordance with the modified pattern.

摘要翻译： FPGA包括主资源和冗余资源。 为了编程FPGA以执行所需的功能，首先准备了仅利用主资源的待编程的可编程元件的模式。 响应于先前获得的关于FPGA内的缺陷的信息来修改该模式。 修改的模式利用冗余资源作为由缺陷引起的不可用的FPGA元素的直接或间接替代。 FPGA根据修改的模式进行编程。

公开(公告)号：US06587992B2

公开(公告)日：2003-07-01

申请号：US10177992

申请日：2002-06-20

申请人： David P. Marple

发明人： David P. Marple

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： The present invention relates to layouts with geometrical objects, and more particularly, to a system and method for compacting layouts in two dimensions simultaneously. In an embodiment, the system and method of the present invention are applied to IC layouts. The present invention provides for compacting layouts in two dimensions at once without depending on expensive methods such as Branch and Bound. As a result, in an embodiment, the present invention can be applied to large layouts in much the same way as conventional, one dimensional compaction systems and methods. The present invention also provides for compacting hierarchical layouts in two dimensions at once while preserving the complete hierarchy.

摘要翻译： 本发明涉及具有几何对象的布局，更具体地，涉及用于同时压缩两维的布局的系统和方法。 在一个实施例中，本发明的系统和方法应用于IC布局。 本发明提供了一次二维地压缩布局，而不依赖诸如分支和边界等昂贵的方法。 结果，在一个实施例中，本发明可以以与传统的一维压实系统和方法大致相同的方式应用于大型布局。 本发明还提供了在保持完整的层次的同时在二维上同时压缩分层布局。