CDR with digitally controlled lock to reference
    2.
    发明授权
    CDR with digitally controlled lock to reference 有权
    具有数字控制锁的CDR以供参考

    公开(公告)号:US08687756B2

    公开(公告)日:2014-04-01

    申请号:US13235628

    申请日:2011-09-19

    IPC分类号: H03D3/24

    摘要: In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.

    摘要翻译: 在所描述的实施例中,接收机包括具有比例和积分环路控制的压控振荡器(VCO)的时钟和数据恢复(CDR)电路,以及使用相位和频率检测器(PFD)控制的锁定到参考(L2R)模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下,结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比,实现了相对较快的锁定参考。

    CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE
    3.
    发明申请
    CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE 有权
    具有数字控制的CDR锁定参考

    公开(公告)号:US20130070835A1

    公开(公告)日:2013-03-21

    申请号:US13235628

    申请日:2011-09-19

    IPC分类号: H04L27/06 H03K9/08

    摘要: In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.

    摘要翻译: 在所描述的实施例中,接收机包括具有比例和积分环路控制的压控振荡器(VCO)的时钟和数据恢复(CDR)电路,以及使用相位和频率检测器(PFD)控制的锁定到参考(L2R)模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下,结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比,实现了相对较快的锁定参考。

    Golf putting trainer
    5.
    发明授权
    Golf putting trainer 失效
    高尔夫球练习器

    公开(公告)号:US5409231A

    公开(公告)日:1995-04-25

    申请号:US170067

    申请日:1993-12-20

    IPC分类号: A63B69/36

    摘要: A putting accuracy training aid providing an elongated, flat rolling surface and a non-slip base. A recessed tee supports a ball forward of an adjustable stroke gauge and elastomer limit stop. Inclined surfaces, projections and/or grooves provided adjacent the tee facilitate re-teeing without stooping. Jointed multi-section constructions are also disclosed having a sectional body and/or wing attachments.

    摘要翻译: 放置精度训练辅助器提供细长的平坦滚动表面和防滑底座。 一个凹陷的三通支撑一个可调节的行程计和弹性体极限挡块的前方的球。 与三通相邻设置的倾斜表面,突起和/或凹槽有助于在没有弯曲的情况下重新起泡。 还公开了具有截面体和/或翼附件的接合多段结构。

    Combined differential and single-ended input buffer
    6.
    发明授权
    Combined differential and single-ended input buffer 失效
    组合差分和单端输入缓冲器

    公开(公告)号:US06683484B1

    公开(公告)日:2004-01-27

    申请号:US10324284

    申请日:2002-12-19

    IPC分类号: H03F345

    摘要: An integrated circuit input buffer is provided, which includes a differential buffer, first and second average value circuits and a feedback amplifier. The input buffer is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.

    摘要翻译: 提供了一种集成电路输入缓冲器,其包括差分缓冲器,第一和第二平均值电路和反馈放大器。 输入缓冲器可选择性地在差分工作模式和单端操作模式下工作。 差分放大器具有第一和第二缓冲器输入以及第一和第二缓冲器输出。 第一和第二平均值电路分别具有耦合到第一和第二缓冲器输出的输入。 反馈放大器具有分别耦合到第一和第二平均值电路的输出的第一和第二差分输入,并且具有放大器输出。 当输入缓冲器处于单端操作模式时,放大器输出耦合到第二缓冲器输入端,并且当输入缓冲器处于差分工作模式时与第二缓冲器输入端分离。

    Method of making SOI circuit for higher temperature and higher voltage
applications
    7.
    发明授权
    Method of making SOI circuit for higher temperature and higher voltage applications 失效
    制造更高温度和更高电压应用的SOI电路的方法

    公开(公告)号:US5893729A

    公开(公告)日:1999-04-13

    申请号:US671100

    申请日:1996-06-28

    摘要: Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

    摘要翻译: 在位于下面的掩埋氧化物层之上的硅层中形成CMOS晶体管的方法,包括隔离第一有源区和第二有源区; 形成具有指定的栅极阈值电压的n阱和p阱; 在井上形成闸门; 在穿过硅层的p阱中形成轻掺杂的漏极区; 以及注入离子以在p阱中形成源区和漏区,以提供轻掺杂漏极漂移区。