-
公开(公告)号：US20130070835A1
公开(公告)日：2013-03-21
申请号：US13235628
申请日：2011-09-19
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译： 在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。
-
公开(公告)号：US08687756B2
公开(公告)日：2014-04-01
申请号：US13235628
申请日：2011-09-19
IPC分类号： H03D3/24
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译： 在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。
-
3.发明申请公开(公告)号：US20120027073A1
公开(公告)日：2012-02-02
申请号：US12847700
申请日：2010-07-30
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0356 , H04L2025/03617 , H04L2025/03796
摘要： Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
摘要翻译： 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时，使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式，以确保当修正了极点和增益中的相应一个时，错误样本中的明确的变化方向。
-
4.发明授权Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns 失效具有可编程自适应模式的连续时间决策反馈均衡器的适应方法和装置公开(公告)号：US08483266B2
公开(公告)日：2013-07-09
申请号：US12847700
申请日：2010-07-30
申请人： Christopher J. Abel , Lane A. Smith , Philip N. Jenkins , Brett D. Hardy , Vladimir Sindalovsky
发明人： Christopher J. Abel , Lane A. Smith , Philip N. Jenkins , Brett D. Hardy , Vladimir Sindalovsky
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0356 , H04L2025/03617 , H04L2025/03796
摘要： Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
摘要翻译： 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时，使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式，以确保当修正了极点和增益中的相应一个时，错误样本中的明确的变化方向。
-
公开(公告)号：US20130009679A1
公开(公告)日：2013-01-10
申请号：US13178812
申请日：2011-07-08
申请人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
发明人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
IPC分类号： H03L7/06
摘要： In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.
摘要翻译： 在所描述的实施例中，具有数字爆炸相位检测器（BBPD）的时钟对准系统采用数字实现的滞后。 第一个BBPD被用于相位控制环路，该相位控制环路比较来自两个不同时钟域源的相位，其中一个时钟源源作为相位控制环路的参考时钟。 采用具有延迟参考时钟的第二个BBPD来解决第一个BBPD所看到的模糊相位关系。 检查被定义为第一BBPD和第二BBPD的当前值的矢量的BBPD矢量的初始状态。 基于BBPD矢量的初始状态和后续状态，允许非参考时钟通过相位控制回路的动作自然地移动到锁定状态，或者被迫使其相位顺时针或逆时针旋转以达到锁定状态。
-
公开(公告)号：US08067966B2
公开(公告)日：2011-11-29
申请号：US10999900
申请日：2004-11-30
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译： 公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。 电压控制延迟环路产生具有相似频率和不同相位的时钟信号。 电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。 多个延迟元件串联连接，例如循环。 在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。
-
7.发明授权公开(公告)号：US07965133B2
公开(公告)日：2011-06-21
申请号：US12160373
申请日：2007-10-31
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译： 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。
-
公开(公告)号：US07773667B2
公开(公告)日：2010-08-10
申请号：US11181286
申请日：2005-07-14
CPC分类号： G01R31/31715
摘要： The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
摘要翻译： 本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置（SERDES）的异步测试的装置，系统和方法。 示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟，其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器，其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。 在另外的实施例中，伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。
-
9.发明授权Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye 失效用于使用单面眼确定用于判决反馈均衡的闩锁位置的方法和装置公开(公告)号：US07711043B2
公开(公告)日：2010-05-04
申请号：US11540946
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.
摘要翻译： 提供了用于确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。 通过约束输入数据来确定由判决反馈均衡器采用的锁存器的阈值位置，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 以及基于所述样本确定所述锁存器的阈值位置。 受约束的输入数据可以包括（i）从二进制值1到二进制值0或1的转换; 或（ii）从二进制值0到二进制值0或1的转换。单面数据眼的大小可以通过分析与单面数据眼相关联的直方图来识别具有 不断的命中数。
-
10.发明授权公开(公告)号：US08165253B2
公开(公告)日：2012-04-24
申请号：US12200106
申请日：2008-08-28
IPC分类号： H04L7/00
CPC分类号： H04J3/0685
摘要： Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.
摘要翻译： 提供串行器/解串器发射机同步的方法和装置。 通过在一个或多个信道中产生同步请求，在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号，仅产生一个同步信号的一个或多个周期的门控同步信号。 门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。
-
-
-
-
-
-
-
-
-
搜索结果
133 条记录 (耗时 0.034 秒)
