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公开(公告)号：US06738248B1
公开(公告)日：2004-05-18
申请号：US10281811
申请日：2002-10-28
IPC分类号： H02H322
CPC分类号： H01L27/0255
摘要： An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.
摘要翻译： 提供了一种过电压保护的集成电路，其包括放电节点，输入 - 输出焊盘，耦合到输入 - 输出焊盘的信号迹线以及一对背对背二极管，其耦合 在第一信号迹线和放电节点之间。
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公开(公告)号：US08687756B2
公开(公告)日：2014-04-01
申请号：US13235628
申请日：2011-09-19
IPC分类号： H03D3/24
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译： 在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。
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公开(公告)号：US20130070835A1
公开(公告)日：2013-03-21
申请号：US13235628
申请日：2011-09-19
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译： 在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。
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公开(公告)号：US07342977B2
公开(公告)日：2008-03-11
申请号：US10304922
申请日：2002-11-26
CPC分类号： H04L25/4908 , H04L5/1446
摘要： A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.
摘要翻译： 提供了一种传输串行数据的方法。 该方法包括接收连续的发送数据字，其中每个发送数据字具有多个位。 每个发送数据字中的多个比特中的每一个被乘以多个相邻比特以形成扩展数据字。 扩展数据字中的每一个被串行化以形成串行数据字流，并被发送。
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5.发明授权Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns 失效具有可编程自适应模式的连续时间决策反馈均衡器的适应方法和装置公开(公告)号：US08483266B2
公开(公告)日：2013-07-09
申请号：US12847700
申请日：2010-07-30
申请人： Christopher J. Abel , Lane A. Smith , Philip N. Jenkins , Brett D. Hardy , Vladimir Sindalovsky
发明人： Christopher J. Abel , Lane A. Smith , Philip N. Jenkins , Brett D. Hardy , Vladimir Sindalovsky
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0356 , H04L2025/03617 , H04L2025/03796
摘要： Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
摘要翻译： 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时，使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式，以确保当修正了极点和增益中的相应一个时，错误样本中的明确的变化方向。
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6.发明申请公开(公告)号：US20120027073A1
公开(公告)日：2012-02-02
申请号：US12847700
申请日：2010-07-30
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0356 , H04L2025/03617 , H04L2025/03796
摘要： Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
摘要翻译： 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时，使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式，以确保当修正了极点和增益中的相应一个时，错误样本中的明确的变化方向。
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公开(公告)号：US6114982A
公开(公告)日：2000-09-05
申请号：US105702
申请日：1998-06-26
申请人： Brett D. Hardy , Alan S. Fiedler
发明人： Brett D. Hardy , Alan S. Fiedler
CPC分类号： H03M1/0682 , H03M1/365
摘要： An analog-to-digital (A/D) converter for converting an analog signal into a digital signal includes a first resistor ladder coupled between a first reference voltage and a second reference voltage. The A/D converter also includes a second resistor ladder that matches the first resistor ladder and that has a first end and a second end coupled to an analog signal source. The first resistor ladder and the second resistor ladder are coupled to at least two comparators with each comparator having a reference input and an analog input. The impedance at each reference input due to the first resistor ladder matches the impedance at each corresponding analog input due to the second resistor ladder.
摘要翻译： 用于将模拟信号转换为数字信号的模数（A / D）转换器包括耦合在第一参考电压和第二参考电压之间的第一电阻器梯形。 A / D转换器还包括与第一电阻梯相匹配的第二电阻梯，其具有耦合到模拟信号源的第一端和第二端。 第一电阻梯和第二电阻梯耦合到至少两个比较器，每个比较器具有参考输入和模拟输入。 由于第一个电阻梯形图，每个参考输入端的阻抗与每个相应的模拟输入端的阻抗相匹配，这是由于第二个电阻梯。
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公开(公告)号：US5955978A
公开(公告)日：1999-09-21
申请号：US925041
申请日：1997-09-08
申请人： Alan S. Fiedler , Brett D. Hardy
发明人： Alan S. Fiedler , Brett D. Hardy
CPC分类号： H03M1/1023 , H03M1/12
摘要： An A/D converter has an auto-zeroed latching comparator with an input offset voltage. The latching comparator is repetitively switched between an offset adjustment mode and a conversion mode. When the comparator is in the offset adjustment mode, the comparator compares the reference voltage to itself and generates an offset measurement output based on the comparison. A feedback circuit adjusts the input offset voltage based on the offset measurement output. When the comparator is in the conversion mode, the comparator compares the input signal to the reference voltage and generates the digital output signal based on the comparison.
摘要翻译： A / D转换器具有自动归零锁存比较器，具有输入失调电压。 锁存比较器在偏移调整模式和转换模式之间重复切换。 当比较器处于偏移调整模式时，比较器将参考电压与其自身进行比较，并根据比较产生偏移测量输出。 反馈电路根据偏移测量输出调整输入失调电压。 当比较器处于转换模式时，比较器将输入信号与参考电压进行比较，并根据比较产生数字输出信号。
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公开(公告)号：US06731683B1
公开(公告)日：2004-05-04
申请号：US09677269
申请日：2000-10-02
申请人： Alan S. Fiedler , Brett D. Hardy
发明人： Alan S. Fiedler , Brett D. Hardy
IPC分类号： H03H730
CPC分类号： H04L25/03159 , H04L1/203 , H04L7/0058 , H04L7/0331 , H04L2025/03738
摘要： A serial data communication receiver includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of the first equalizer to one of the frequency response settings based on the measured data eye sizes.
摘要翻译： 串行数据通信接收机包括串行数据输入，第一和第二均衡器，第一和第二捕捉锁存电路以及均衡控制电路。 第一和第二均衡器耦合到串行数据输入端，分别具有第一和第二均衡串行数据输出。 每个均衡器具有频率响应，频率响应在频率响应设置的范围内是可变的。 第一和第二捕捉锁存电路分别在锁相环中耦合到第一和第二均衡的串行数据输出，并且分别具有第一和第二恢复的数据输出。 均衡控制电路测量第二均衡器的频率响应设置范围上的第二均衡串行数据输出的数据眼尺寸，并且基于所测量的数据眼尺寸将第一均衡器的频率响应设置为频率响应设置之一 。
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公开(公告)号：US06417790B1
公开(公告)日：2002-07-09
申请号：US09782806
申请日：2001-02-14
申请人： Alan S. Fiedler , Brett D. Hardy
发明人： Alan S. Fiedler , Brett D. Hardy
IPC分类号： H03M900
CPC分类号： H03M9/00 , H03K17/04106 , H03K17/693
摘要： A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs. Each pair of first and second control inputs is driven by first and second logic AND circuits having p-channel output drive transistors.
摘要翻译： 数据串行器包括差分输出级。 差分输出级具有n对第一和第二控制输入，其中每对控制输入对应于n个数据输入之一。 每对第一和第二控制输入由具有p沟道输出驱动晶体管的第一和第二逻辑与电路驱动。
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