公开(公告)号：US20080205454A1

公开(公告)日：2008-08-28

申请号：US11821660

申请日：2007-06-25

申请人： Michael Riedel ,  Roland Neumann

发明人： Michael Riedel ,  Roland Neumann

IPC分类号： H04J3/06

CPC分类号： H04J3/0605 ,  H04L25/4915

摘要： A serial data frame has a payload data frame and a synchronization frame. In addition to transmitting payload data in the payload data frame, payload data is also transmitted in the synchronization frame. Special bit patterns are transmitted in the synchronization frame at predetermined times. The synchronization of the transmission of the serial data frame is performed by indicating the sequence of the bit patterns and their position in the synchronization frame to both the transmitter and the receiver of the serial data frame. Furthermore, payload data is masked using a logical operation so that a maximum permitted length of consecutive bits of the same value is avoided.

摘要翻译： 串行数据帧具有有效载荷数据帧和同步帧。 除了在有效载荷数据帧中发送有效载荷数据之外，还在同步帧中传送有效载荷数据。 在同步帧中以预定的时间发送特殊位模式。 串行数据帧的发送的同步通过指示位模式的顺序及其在同步帧中对串行数据帧的发送器和接收器的位置的顺序来执行。 此外，使用逻辑操作掩蔽有效载荷数据，使得避免了相同值的连续比特的最大允许长度。

公开(公告)号：US20060176934A1

公开(公告)日：2006-08-10

申请号：US11341346

申请日：2006-01-26

申请人： Michael Riedel ,  Roland Neumann

发明人： Michael Riedel ,  Roland Neumann

IPC分类号： H04B1/69

CPC分类号： H04B1/69 ,  H03L7/197 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

摘要： An apparatus for serial transmission of data over a transmission path in a vehicle uses spread-spectrum modulation to enhance the electromagnetic compatibility with other electrical and electronic components in the vehicle. The apparatus includes a transmitter that subjects a clock signal having a predetermined frequency and phase to spread-spectrum modulation by wobbling a first clock signal within a predetermined frequency range. The serial data signal is transmitted synchronously with the wobbled first clock signal. The apparatus includes a receiver that uses a blind-oversampling clock and data retrieving unit (CDR unit) to receive the serial data signal. The receiver also generates multiple second clock signals. The CDR unit uses a predetermined algorithm to output the best-suited one of several oversampled serial data signals synchronously with a selected one of the second clock signals. A corresponding method is disclosed for serial transmission of data using spread-spectrum modulation to enhance electromagnetic compatibility.

摘要翻译： 用于在车辆的传输路径上串行传输数据的装置使用扩频调制来提高与车辆中的其它电气和电子部件的电磁兼容性。 该装置包括发射机，其通过在预定频率范围内摆动第一时钟信号来对具有预定频率和相位的时钟信号进行扩频调制。 串行数据信号与摆动的第一时钟信号同步发送。 该装置包括使用盲过采样时钟和数据检索单元（CDR单元）接收串行数据信号的接收机。 接收机还产生多个第二时钟信号。 CDR单元使用预定算法与所选择的第二时钟信号同步地输出几个过采样串行数据信号中最适合的一个。 公开了使用扩频调制串行传输数据以增强电磁兼容性的相应方法。

公开(公告)号：US20060164266A1

公开(公告)日：2006-07-27

申请号：US11386559

申请日：2006-03-22

申请人： Michael Riedel ,  Roland Neumann

发明人： Michael Riedel ,  Roland Neumann

IPC分类号： H03M7/00

CPC分类号： H04N21/242 ,  H04J3/0632 ,  H04N21/4305 ,  H04N21/8547

摘要： A system synthesizes a remote controlled clock across data transmission through a digital multimedia link. A clock is generated at the receiver side that is exactly synchronous to a master clock at the transmitter side. The system includes a clock encoder on the transmitter side, a synchronous serial data transmission system, and a clock decoder on the receiver side. The clock encoder and decoder include counters that count up until predetermined numbers are exceeded and wrap around when those predetermined numbers are exceeded. A clock synthesizer in the clock decoder generates the remote controlled clock. A controller in the clock decoder processes remote and local time stamps and generates control signals that control the clock synthesizer such that the remote controlled clock has the same frequency and the same number of transitions as the master clock received by the clock encoder.

摘要翻译： 系统通过数字多媒体链路综合跨数据传输的远程控制时钟。 在接收机侧产生与发射机侧的主时钟精确同步的时钟。 该系统包括发射机侧的时钟编码器，同步串行数据传输系统和接收机侧的时钟解码器。 时钟编码器和解码器包括计数器，直到超过预定数量为止，并且当超过这些预定数量时循环。 时钟解码器中的时钟合成器产生远程控制时钟。 时钟解码器中的控制器处理远程和本地时间戳，并且产生控制时钟合成器的控制信号，使得遥控时钟具有与时钟编码器接收的主时钟相同的频率和相同数量的转换。

公开(公告)号：US08000350B2

公开(公告)日：2011-08-16

申请号：US11386542

申请日：2006-03-22

申请人： Michael Riedel ,  Roland Neumann

发明人： Michael Riedel ,  Roland Neumann

IPC分类号： H04J3/06

CPC分类号： H04J3/1605 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/10 ,  H04J3/0605 ,  H04L7/00 ,  H04N21/242

摘要： A system for reducing the bandwidth of a data stream transmitted via a digital multimedia link does not result in the loss of data. The system encodes control signals such that control words are generated each time the status of the control signals change. The system multiplexes payload data and the control words to generate the data stream. If no blanking period of the payload data is present, the data stream comprises payload data. During the blanking period, the data stream comprises the control words. The data stream is transmitted across the digital multimedia link using transmit and receive FIFO memories. The transmitted data stream is then demultiplexed, and the payload data and the control words are separated from each other. The control words are decoded to recover the control signals. The system can transmit payload data conforming to the video formats VGA, SVGA, XGA, SXGA and UXGA.

摘要翻译： 用于减少通过数字多媒体链路发送的数据流的带宽的系统不会导致数据丢失。 该系统对控制信号进行编码，以便每当控制信号的状态改变时产生控制字。 系统复用有效载荷数据和控制字以产生数据流。 如果不存在有效载荷数据的消隐期，则数据流包括有效载荷数据。 在消隐期间，数据流包括控制字。 使用发送和接收FIFO存储器在数字多媒体链路上传输数据流。 然后将发送的数据流解复用，并且将有效载荷数据和控制字彼此分离。 控制字被解码以恢复控制信号。 该系统可以传输符合视频格式VGA，SVGA，XGA，SXGA和UXGA的有效载荷数据。

公开(公告)号：US20060179201A1

公开(公告)日：2006-08-10

申请号：US11386542

申请日：2006-03-22

申请人： Michael Riedel ,  Roland Neumann

发明人： Michael Riedel ,  Roland Neumann

IPC分类号： G06F13/14

CPC分类号： H04J3/1605 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/10 ,  H04J3/0605 ,  H04L7/00 ,  H04N21/242

摘要： A system for reducing the bandwidth of a data stream transmitted via a digital multimedia link does not result in the loss of data. The system encodes control signals such that control words are generated each time the status of the control signals change. The system multiplexes payload data and the control words to generate the data stream. If no blanking period of the payload data is present, the data stream comprises payload data. During the blanking period, the data stream comprises the control words. The data stream is transmitted across the digital multimedia link using transmit and receive FIFO memories. The transmitted data stream is then demultiplexed, and the payload data and the control words are separated from each other. The control words are decoded to recover the control signals. The system can transmit payload data conforming to the video formats VGA, SVGA, XGA, SXGA and UXGA.

摘要翻译： 用于减少通过数字多媒体链路发送的数据流的带宽的系统不会导致数据丢失。 该系统对控制信号进行编码，以便每当控制信号的状态改变时产生控制字。 系统复用有效载荷数据和控制字以产生数据流。 如果不存在有效载荷数据的消隐期，则数据流包括有效载荷数据。 在消隐期间，数据流包括控制字。 使用发送和接收FIFO存储器在数字多媒体链路上传输数据流。 然后将发送的数据流解复用，并且将有效载荷数据和控制字彼此分离。 控制字被解码以恢复控制信号。 该系统可以传输符合视频格式VGA，SVGA，XGA，SXGA和UXGA的有效载荷数据。

公开(公告)号：US06181757B2

公开(公告)日：2001-01-30

申请号：US09067757

申请日：1998-04-27

申请人： Roland Neumann ,  Phil Jeffery ,  David Ford

发明人： Roland Neumann ,  Phil Jeffery ,  David Ford

IPC分类号： H03D324

CPC分类号： H04L7/0338 ,  G06F1/025 ,  H03L7/06

摘要： Retiming means for retiming an incoming data stream 2 comprising clock generation means 22 for producing a plurality of clock signals 23 having the same frequency but differing phase, and signal processing means 24 for receiving both the plurality of clock signals 23 and the incoming data stream 2 and outputting a selected one of the clock signals 23 and a retimed data stream retimed in accordance with the selected clock signal. The signal processing means 24 includes comparison means for comparing the phase of the incoming data stream with the phase of the plurality of clock signals and selecting which clock signal to use on the basis of this comparison.

摘要翻译： 重新定时装置，用于重新定时输入数据流2，包括时钟产生装置22，用于产生具有相同频率但不同相位的多个时钟信号23;以及信号处理装置24，用于接收多个时钟信号23和输入数据流2 并输出所选择的一个时钟信号23和根据所选时钟信号重新定时的重新定时数据流。 信号处理装置24包括比较装置，用于将输入数据流的相位与多个时钟信号的相位进行比较，并且基于该比较选择使用哪个时钟信号。