-
公开(公告)号：US20110115537A1
公开(公告)日：2011-05-19
申请号：US12621050
申请日：2009-11-18
IPC分类号： H03K5/12
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译： 实施例包括用于对输入信号进行重新计时的电路装置和方法。 在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。 数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。
-
2.发明申请TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME 审中-公开具有片间传输器的调谐电路和提供互连链路帧的方法公开(公告)号：US20110158298A1
公开(公告)日：2011-06-30
申请号：US12649911
申请日：2009-12-30
申请人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
发明人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
CPC分类号： H04B1/38
摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.
摘要翻译： 调谐器电路包括数字信号处理器，用于产生与射频信号相关的数字数据流，以及耦合到数字信号处理器的收发器电路，并且可配置为产生具有起始部分和多个通道的芯片间通信帧。 多个信道包括携带数字数据流的一部分的第一数据信道和用于携带控制数据的控制信道。 收发器电路可配置为通过芯片间通信链路将片间通信帧发送到附加的调谐器电路。
-
公开(公告)号：US09209912B2
公开(公告)日：2015-12-08
申请号：US12621050
申请日：2009-11-18
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译： 实施例包括用于对输入信号进行重新计时的电路装置和方法。 在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。 数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。
-
公开(公告)号：US08548031B2
公开(公告)日：2013-10-01
申请号：US12649761
申请日：2009-12-30
CPC分类号： H04B1/0028 , H04J3/0685
摘要： A tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor synchronizes the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset. The digital signal processor performs a selected antenna diversity operation on the first and second DSP frames to produce an output signal.
摘要翻译： 调谐器电路包括基于第一RF信号产生第一DSP帧的电路，并且包括耦合到芯片间链路并被配置为接收片间帧的芯片间接收器电路。 芯片间接收电路被配置为检测芯片间帧的帧符号的开始，并从芯片间帧提取DSP偏移量和与第二DSP帧有关的数据。 调谐器电路还包括耦合到电路和芯片间接收器电路的数字信号处理器。 数字信号处理器基于帧符号的开始和数字信号处理器的偏移量，将第一DSP帧与第二DSP帧同步。 数字信号处理器在第一和第二DSP帧上执行所选择的天线分集操作以产生输出信号。
-
5.发明申请ANTENNA DIVERSITY SYSTEM WITH MULTIPLE TUNER CIRCUITS HAVING MULTIPLE OPERATING MODES AND METHODS 有权具有多种操作模式和方法的多个调谐器电路的天线多样性系统公开(公告)号：US20110158339A1
公开(公告)日：2011-06-30
申请号：US12650166
申请日：2009-12-30
申请人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
发明人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
CPC分类号： H04B7/0682 , H04L25/03866
摘要： In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.
摘要翻译： 在一个实施例中，调谐器电路包括可配置为耦合到第一芯片间通信链路以接收第一数据流的芯片间接收器电路，并且包括被配置为将射频信号转换为数字 版本的射频信号。 调谐器电路还包括耦合到芯片间接收器电路和模数转换器的数字信号处理器。 数字信号处理器可配置为基于所选择的操作模式生成与第一数据流和数字版本的数字版本中的至少一个相关的输出信号。
-
公开(公告)号：US20110158357A1
公开(公告)日：2011-06-30
申请号：US12649761
申请日：2009-12-30
IPC分类号： H04L27/06
CPC分类号： H04B1/0028 , H04J3/0685
摘要： In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal.
摘要翻译： 在一个实施例中，调谐器电路包括基于第一RF信号产生第一DSP帧的电路，并且包括耦合到芯片间链路并被配置为接收片间帧的片间接收器电路。 芯片间接收电路被配置为检测芯片间帧的帧符号的开始，并从芯片间帧提取DSP偏移量和与第二DSP帧有关的数据。 调谐器电路还包括耦合到电路和芯片间接收器电路的数字信号处理器。 数字信号处理器将基于帧符号开始和数字信号处理器偏移来同步第一DSP帧与第二DSP帧，数字信号处理器被配置为在第一和第二DSP帧上执行所选择的天线分集操作， 产生输出信号。
-
7.发明授权Antenna diversity system with multiple tuner circuits having multiple operating modes and methods 有权具有多个调谐器电路的天线分集系统具有多种操作模式和方法公开(公告)号：US08331887B2
公开(公告)日：2012-12-11
申请号：US12650166
申请日：2009-12-30
申请人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
发明人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
CPC分类号： H04B7/0682 , H04L25/03866
摘要： In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.
摘要翻译： 在一个实施例中，调谐器电路包括可配置为耦合到第一芯片间通信链路以接收第一数据流的芯片间接收器电路，并且包括被配置为将射频信号转换为数字 版本的射频信号。 调谐器电路还包括耦合到芯片间接收器电路和模数转换器的数字信号处理器。 数字信号处理器可配置为基于所选择的操作模式生成与第一数据流和数字版本的数字版本中的至少一个相关的输出信号。
-
8.发明申请TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME 审中-公开具有片间传输器的调谐电路和提供互连链路帧的方法公开(公告)号：US20120099625A1
公开(公告)日：2012-04-26
申请号：US13342619
申请日：2012-01-03
申请人： Younes Djadi , Scott Thomas Haban
发明人： Younes Djadi , Scott Thomas Haban
IPC分类号： H04B1/38
CPC分类号： H04B1/38
摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame including a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a high definition intermediate frequency signal and including a second data channel to carry a demodulated audio signal, the transceiver circuit configurable to provide the inter-chip communication frame to an inter-chip communication link.
摘要翻译： 调谐器电路包括：数字信号处理器，用于产生与射频信号相关的数字数据流;以及收发器电路，耦合到数字信号处理器，并可配置为产生包括起始部分和多个通道的芯片间通信帧。 多个信道包括携带高清晰度中频信号的第一数据信道，并且包括第二数据信道以携带解调的音频信号，所述收发器电路可配置为将芯片间通信帧提供给芯片间通信链路。
-
公开(公告)号：US06661891B1
公开(公告)日：2003-12-09
申请号：US09498435
申请日：2000-02-04
申请人： Younes Djadi , Vijayakumaran V. Nair , Yan Zhou
发明人： Younes Djadi , Vijayakumaran V. Nair , Yan Zhou
IPC分类号： H04M100
CPC分类号： H04M3/2272 , H04M3/007 , H04Q1/46
摘要： A line card for interfacing with a plurality of subscriber lines includes a plurality of data processors and a tone detector. Each of the data processors is associated with one of the subscriber lines. The tone detector is adapted to detect one of a plurality of activation tones on a selected subscriber line. The plurality of activation tones include a first activation tone having an active portion and a silent portion. The active and silent portions repeat periodically at a first frequency having a first period. A second activation tone has a phase reversal portion repeating at a second frequency and having a second period. The tone detector is further adapted to sequence between the subscriber lines at a predetermined interval. The predetermined interval is based on the first and second periods. The tone detector is adapted to signal the data processor associated with the selected subscriber line in response to detecting one of the activation tones.
摘要翻译： 用于与多个用户线路连接的线路卡包括多个数据处理器和音调检测器。 每个数据处理器与一条用户线路相关联。 音调检测器适于检测所选用户线路上的多个激活音调中的一个。 多个激活音包括具有有效部分和无声部分的第一激活音调。 有源和无声部分以具有第一周期的第一频率周期性地重复。 第二激活音具有在第二频率处重复并具有第二周期的相位反转部分。 音调检测器还适于以预定间隔在用户线之间进行序列化。 预定间隔基于第一和第二周期。 响应于检测到激活音中的一个，音调检测器适于发信号通知与选择的用户线相关联的数据处理器。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.026 秒)
