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公开(公告)号：US08548031B2
公开(公告)日：2013-10-01
申请号：US12649761
申请日：2009-12-30
CPC分类号： H04B1/0028 , H04J3/0685
摘要： A tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor synchronizes the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset. The digital signal processor performs a selected antenna diversity operation on the first and second DSP frames to produce an output signal.
摘要翻译： 调谐器电路包括基于第一RF信号产生第一DSP帧的电路，并且包括耦合到芯片间链路并被配置为接收片间帧的芯片间接收器电路。 芯片间接收电路被配置为检测芯片间帧的帧符号的开始，并从芯片间帧提取DSP偏移量和与第二DSP帧有关的数据。 调谐器电路还包括耦合到电路和芯片间接收器电路的数字信号处理器。 数字信号处理器基于帧符号的开始和数字信号处理器的偏移量，将第一DSP帧与第二DSP帧同步。 数字信号处理器在第一和第二DSP帧上执行所选择的天线分集操作以产生输出信号。
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公开(公告)号：US20110158357A1
公开(公告)日：2011-06-30
申请号：US12649761
申请日：2009-12-30
IPC分类号： H04L27/06
CPC分类号： H04B1/0028 , H04J3/0685
摘要： In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal.
摘要翻译： 在一个实施例中，调谐器电路包括基于第一RF信号产生第一DSP帧的电路，并且包括耦合到芯片间链路并被配置为接收片间帧的片间接收器电路。 芯片间接收电路被配置为检测芯片间帧的帧符号的开始，并从芯片间帧提取DSP偏移量和与第二DSP帧有关的数据。 调谐器电路还包括耦合到电路和芯片间接收器电路的数字信号处理器。 数字信号处理器将基于帧符号开始和数字信号处理器偏移来同步第一DSP帧与第二DSP帧，数字信号处理器被配置为在第一和第二DSP帧上执行所选择的天线分集操作， 产生输出信号。
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3.发明申请TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME 审中-公开具有片间传输器的调谐电路和提供互连链路帧的方法公开(公告)号：US20110158298A1
公开(公告)日：2011-06-30
申请号：US12649911
申请日：2009-12-30
申请人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
发明人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
CPC分类号： H04B1/38
摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.
摘要翻译： 调谐器电路包括数字信号处理器，用于产生与射频信号相关的数字数据流，以及耦合到数字信号处理器的收发器电路，并且可配置为产生具有起始部分和多个通道的芯片间通信帧。 多个信道包括携带数字数据流的一部分的第一数据信道和用于携带控制数据的控制信道。 收发器电路可配置为通过芯片间通信链路将片间通信帧发送到附加的调谐器电路。
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4.发明申请ANTENNA DIVERSITY SYSTEM WITH MULTIPLE TUNER CIRCUITS HAVING MULTIPLE OPERATING MODES AND METHODS 有权具有多种操作模式和方法的多个调谐器电路的天线多样性系统公开(公告)号：US20110158339A1
公开(公告)日：2011-06-30
申请号：US12650166
申请日：2009-12-30
申请人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
发明人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
CPC分类号： H04B7/0682 , H04L25/03866
摘要： In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.
摘要翻译： 在一个实施例中，调谐器电路包括可配置为耦合到第一芯片间通信链路以接收第一数据流的芯片间接收器电路，并且包括被配置为将射频信号转换为数字 版本的射频信号。 调谐器电路还包括耦合到芯片间接收器电路和模数转换器的数字信号处理器。 数字信号处理器可配置为基于所选择的操作模式生成与第一数据流和数字版本的数字版本中的至少一个相关的输出信号。
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5.发明授权Antenna diversity system with multiple tuner circuits having multiple operating modes and methods 有权具有多个调谐器电路的天线分集系统具有多种操作模式和方法公开(公告)号：US08331887B2
公开(公告)日：2012-12-11
申请号：US12650166
申请日：2009-12-30
申请人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
发明人： George Tyson Tuttle , Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Lokesh Duraiappah
CPC分类号： H04B7/0682 , H04L25/03866
摘要： In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.
摘要翻译： 在一个实施例中，调谐器电路包括可配置为耦合到第一芯片间通信链路以接收第一数据流的芯片间接收器电路，并且包括被配置为将射频信号转换为数字 版本的射频信号。 调谐器电路还包括耦合到芯片间接收器电路和模数转换器的数字信号处理器。 数字信号处理器可配置为基于所选择的操作模式生成与第一数据流和数字版本的数字版本中的至少一个相关的输出信号。
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公开(公告)号：US20110115537A1
公开(公告)日：2011-05-19
申请号：US12621050
申请日：2009-11-18
IPC分类号： H03K5/12
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译： 实施例包括用于对输入信号进行重新计时的电路装置和方法。 在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。 数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。
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公开(公告)号：US09209912B2
公开(公告)日：2015-12-08
申请号：US12621050
申请日：2009-11-18
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译： 实施例包括用于对输入信号进行重新计时的电路装置和方法。 在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。 数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。
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8.发明申请TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME 审中-公开具有片间传输器的调谐电路和提供互连链路帧的方法公开(公告)号：US20120099625A1
公开(公告)日：2012-04-26
申请号：US13342619
申请日：2012-01-03
申请人： Younes Djadi , Scott Thomas Haban
发明人： Younes Djadi , Scott Thomas Haban
IPC分类号： H04B1/38
CPC分类号： H04B1/38
摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame including a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a high definition intermediate frequency signal and including a second data channel to carry a demodulated audio signal, the transceiver circuit configurable to provide the inter-chip communication frame to an inter-chip communication link.
摘要翻译： 调谐器电路包括：数字信号处理器，用于产生与射频信号相关的数字数据流;以及收发器电路，耦合到数字信号处理器，并可配置为产生包括起始部分和多个通道的芯片间通信帧。 多个信道包括携带高清晰度中频信号的第一数据信道，并且包括第二数据信道以携带解调的音频信号，所述收发器电路可配置为将芯片间通信帧提供给芯片间通信链路。
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公开(公告)号：US08831521B2
公开(公告)日：2014-09-09
申请号：US12975334
申请日：2010-12-21
CPC分类号： H04B1/1036
摘要： A circuit includes an input terminal for receiving a radio frequency (RF) signal and a noise mitigation circuit coupled to the input terminal. The noise mitigation circuit is configured to detect a low-frequency noise signature in the RF signal and to automatically adjust an attenuation network to filter low-frequency noise from the RF signal in response to detecting the low-frequency noise signature.
摘要翻译： 电路包括用于接收射频（RF）信号的输入端和耦合到输入端的噪声抑制电路。 噪声消除电路被配置为检测RF信号中的低频噪声特征，并且响应于检测到低频噪声特征而自动调整衰减网络以从RF信号滤波低频噪声。
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公开(公告)号：US6055619A
公开(公告)日：2000-04-25
申请号：US797232
申请日：1997-02-07
申请人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
发明人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275
摘要： An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.
摘要翻译： 公开了一种音频信息处理子系统200，其包括用于同时处理多个音频数据流的流处理器100。 处理子系统200还包括耦合到流处理器100的程序存储器202，用于存储用于控制处理系统200的指令和还耦合到流处理器100的数据存储器203/204。另外，提供直接存储器访问电路208用于控制直接存储器 访问程序存储器202和数据存储器203/204中的所选择的一个。
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