公开(公告)号：US07020757B2

公开(公告)日：2006-03-28

申请号：US10400371

申请日：2003-03-27

申请人： Michael Ruhovets ,  Christopher C. Wanner

发明人： Michael Ruhovets ,  Christopher C. Wanner

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/4278 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by another point-to-point link to another memory module. Further memory modules may be coupled by respective point-to-point links in the memory subsystem. In some arrangements, each memory module tracks commands issued to other memory modules, such as more upstream memory modules. Also, in one example implementation, a clock is embedded within a data stream transmitted over a point-to-point link, so that an external clock is not employed in this example implementation.

摘要翻译： 存储器子系统包括通过点对点链接耦合的多个存储器模块。 存储器控制器通过点对点链路耦合到第一存储器模块，第一存储器模块通过另一个点到点链路耦合到另一个存储器模块。 另外的存储器模块可以通过存储器子系统中的相应点对点链路耦合。 在一些布置中，每个存储器模块跟踪发给其他存储器模块的命令，诸如更上游的存储器模块。 此外，在一个示例实现中，时钟被嵌入在通过点对点链路传输的数据流中，使得在该示例实现中不使用外部时钟。

公开(公告)号：US07139859B2

公开(公告)日：2006-11-21

申请号：US10039130

申请日：2001-12-31

申请人： Jaideep Dastidar ,  Ryan J. Hensley ,  Michael Ruhovets ,  An H. Lam

发明人： Jaideep Dastidar ,  Ryan J. Hensley ,  Michael Ruhovets ,  An H. Lam

IPC分类号： G06F13/36

CPC分类号： G06F13/4059

摘要： A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

公开(公告)号：US5087900A

公开(公告)日：1992-02-11

申请号：US615477

申请日：1990-11-19

申请人： James R. Birchak ,  Wai-Leung Hon ,  Michael Ruhovets

发明人： James R. Birchak ,  Wai-Leung Hon ,  Michael Ruhovets

IPC分类号： H04L25/02 ,  H03H7/48

CPC分类号： H03H7/48

摘要： An improved transmission line network includes a transmission line connecting a signal source to a plurality of capacitive loads. Preferably, the transmission line is not terminated with its characteristic impedance. The transmission line may include capacitance added for the purpose of smoothing the rising or falling edge of signals distorted by reflections from the far end of the network. In addition, the transmission line network preferably includes resistance added in series with the transmission line for the purpose of dissipating reflections from the far end and thereby reducing distortion upstream from the series resistors. The capacitive loads may be connected to the transmission line through series resistors, the magnitudes of which are selected to obtain uniform rise or fall times at all loads.

摘要翻译： 改进的传输线网络包括将信号源连接到多个容性负载的传输线。 优选地，传输线不以其特性阻抗来终止。 传输线可以包括为了平滑由来自网络的远端的反射而失真的信号的上升沿或下降沿的目的而添加的电容。 此外，传输线网络优选地包括与传输线串联的电阻，用于耗散远端的反射，从而减少串联电阻器上游的失真。 容性负载可以通过串联电阻连接到传输线，其大小被选择以在所有负载下获得均匀的上升或下降时间。